Chip Package ESD Protection Circuit Area Optimization

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Solution Overview

Problem

Conventional chip package structures require multiple electrostatic discharge (ESD) protection circuits, occupying valuable area and increasing the risk of core circuit damage due to ESD, as a single lead is often connected to multiple terminals.

Innovation Solution

A chip package structure with separate leads and interconnection structures that allow one set of ESD protection circuits to effectively protect multiple connection terminals, preventing direct ESD current from reaching the core circuit by routing the current through an independent ESD protection circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple ESD protection circuits are used to protect each connection terminal, then the ESD protection effect is improved, but the area occupied by ESD protection circuits increases

Engineering Contradiction:
ImproveESD protection effectVSAvoidarea occupied by ESD protection circuits
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple ESD protection functions into a single shared ESD protection circuit. The first lead connects to the ESD protection circuit which then connects to multiple connection terminals through separate interconnection structures. This allows one ESD protection circuit to protect multiple terminals simultaneously, reducing the total number of ESD protection circuits needed while maintaining comprehensive protection coverage.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ESD protection circuit is designed with multi-functionality to serve multiple connection terminals. The single ESD protection circuit can handle ESD events from any of the connected terminals by routing ESD current through the shared protection circuit to ground, eliminating the need for dedicated ESD protection circuits at each terminal location.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If a single lead is connected to multiple terminals, then the lead usage efficiency is improved, but the risk of core circuit damage due to ESD increases

Engineering Contradiction:
Improvelead usage efficiencyVSAvoidrisk of core circuit damage due to ESD
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The ESD protection circuit acts as an intermediary between the lead and the core circuit. When ESD current enters through the lead connected to multiple terminals, the protection circuit intercepts and diverts this harmful current to ground before it can reach the core circuit. This intermediary structure allows the lead to efficiently connect multiple terminals while the protection circuit mediates the ESD hazard.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The ESD protection circuit provides preliminary anti-action by being positioned between the lead and core circuit to preemptively block ESD current. The protection circuit is designed to activate before ESD current can damage the core circuit, clamping voltage spikes and diverting current away from sensitive components, thus preventing damage before it occurs.

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If separate leads are used for each connection terminal, then the ESD protection reliability is improved, but the device complexity increases

Engineering Contradiction:
ImproveESD protection reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the connection structure by separating the ESD protection function from the signal/connection function. Different leads are used for different purposes: the first lead is dedicated to ESD protection and connects to the ESD protection circuit, while the second lead is dedicated to signal transmission and connects directly to the core circuit. This segmentation allows each lead to be optimized for its specific function, achieving reliable ESD protection without requiring complex multi-function leads.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9245857B2Chip package
Publication Date: 2016.01.26 NOVATEK MICROELECTRONICS CORP
  • US9245857B2 patent drawing
  • US9245857B2 patent drawing
  • US9245857B2 patent drawing

AI summary

A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.