Ultra-small Chip Package with Extended Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional semiconductor device packaging designs are hindered by the large volume occupied by wire-bonding platforms and lead frames, limiting the miniaturization of semiconductor devices as the size of the die decreases, as these components account for a significant portion of the package volume.
Innovation Solution
The design incorporates a plate-like back electrode and positive electrodes extending beyond the die, which are encapsulated with a plastic layer, allowing for a significant reduction in the overall assembly volume by minimizing the volume occupied by electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding platforms and lead frames are used in traditional packaging, then electrical connections are established, but the package volume is significantly increased
Solution Approach 1:
The patent extracts and eliminates the wire-bonding platform and lead frame structures from the packaging design. Instead, it uses the die's own bonding pads directly as electrical connection points, removing the unnecessary intermediate structures that occupied excessive volume while maintaining reliable electrical connections.
Solution Approach 2:
The bonding pads on the die surface serve multiple functions: they act as both the electrical connection terminals and the mounting interface for the die. This multi-functional design eliminates the need for separate lead frames and wire-bonding platforms, significantly reducing package volume while maintaining connection reliability.
2Volume of moving object
If the die size is reduced to achieve miniaturization, then device size decreases, but the volume ratio of die within package decreases due to fixed lead frame volume
Solution Approach 1:
By removing the lead frame and wire-bonding platform structures, the patent eliminates the fixed minimum volume that constrained die size reduction. This allows the die volume ratio within the package to increase significantly, enabling effective miniaturization even as die dimensions decrease.
Data Source
AI summary
Some embodiments of the present disclosure provide the design and manufacture of an ultra-small chip assembly. The ultra-small chip assembly comprises a die, a plate-like back electrode disposed on the back-side of the die, and one or more plate-like positive electrodes disposed on the front-side of the die. The ultra-small chip assembly is configured such that one end of the plate-like back electrode extends beyond a first side of the die, and each of the one or more plate-like positive electrodes includes an end which extends beyond a second side of the die. By attaching both the plate-like back electrode and the plate-like positive electrodes on the surfaces of the die, and directly using the exposed ends of the plate-like electrodes as the lead-out electrodes for the chip assembly, the electrical connections outside of the die only occupy a very small volume.