Multi-Layer Gap-Filling in Chip Packages for Die Stress Relief

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Solution Overview

Problem

The reliability of protective layers in semiconductor chip packages is compromised due to die-to-die stress and thermal expansion mismatch, leading to potential delamination and cracking, which affects the long-term reliability of the chip package structure.

Innovation Solution

A multi-layer underfill structure with different Young's modulus and thermal expansion coefficients is used to buffer stress between semiconductor dies and the interposer substrate, and an encapsulating layer is formed to surround the dies, enhancing adhesion and reducing stress-related issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protective layers are applied to semiconductor chip packages, then reliability is improved, but stress and thermal expansion mismatch cause delamination and cracking

Engineering Contradiction:

Improvereliability of protective layersVSAvoidadhesion strength of protective layers

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent applies parameter changes by selecting underfill materials with specific thermal expansion coefficients and Young's modulus values that match the semiconductor dies and interposer substrate. This parameter matching reduces thermal stress and prevents delamination while maintaining adhesion strength under temperature cycling conditions.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by applying underfill material specifically in the gap regions between adjacent semiconductor dies, rather than uniformly across the entire package. This targeted application provides stress buffering exactly where die-to-die stress concentrations occur, preventing delamination at critical interfaces.

Inventive Principle:

Principle #3Local quality

2Reliability

If underfill material is used to buffer stress, then delamination is prevented, but manufacturing complexity increases

Engineering Contradiction:

Improveresistance to delaminationVSAvoidcomplexity of package structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces underfill material as an intermediary substance between the semiconductor dies and the surrounding protective layers. This intermediary layer absorbs and distributes stress, preventing direct stress transfer that would cause delamination, while the material itself remains simple in composition and application.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If multiple gap-filling layers with different Young's modulus are used, then stress buffering is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvestress management capabilityVSAvoidprecision of layer formation

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the gap-filling structure into multiple layers with different Young's modulus values. The first gap-filling layer has a higher Young's modulus than the second gap-filling layer, creating a gradient structure that progressively buffers stress from rigid to compliant layers, improving overall stress management while maintaining clear manufacturing specifications for each layer.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces die-to-die stress, prevents delamination, and enhances the long-term reliability of the chip package structure by using underfill material layers with varying Young's modulus and thermal expansion coefficients, and an encapsulating layer to manage thermal expansion mismatch.

Implementation Method 1

A multi-layer underfill structure with different Young's modulus and thermal expansion coefficients is used to buffer stress between semiconductor dies and the interposer substrate

Methodology Applied

Scientific EffectStress buffering: Elasticity

Implementation Method 2

thermal expansion mismatch, leading to potential delamination and cracking

Methodology Applied

Scientific EffectThermal expansion mismatch: Thermal Expansion

Implementation Method 3

an encapsulating layer is formed to surround the dies, enhancing adhesion and reducing stress-related issues

Methodology Applied

Scientific EffectAdhesion: Adhesive

Data Source

PatentUS12057363B2Chip package structure with multiple gap-filling layers and fabricating method thereof

Publication Date: 2024.08.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.