Semiconductor Chip Package Ground Via Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor chip packages leads to increased electrical coupling and signal interference between metal lines, necessitating the use of ground vias, which requires additional mask and litho-etching processes, thereby increasing fabrication costs.
Innovation Solution
A semiconductor chip package design that includes a semiconductor chip with sensor devices and connecting pads, featuring vias that are formed without extra mask and litho-etching processes, utilizing an isolation layer and redistribution layer to create a ground via without additional processing steps, and a packaging layer with solder balls for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground vias are fabricated using extra mask and litho-etching processes, then electrical coupling and signal interference issues are resolved, but fabrication cost increases
Solution Approach 1:
The patent combines the formation of ground vias with the existing via formation process for connecting pads. By using the same mask and litho-etching steps that create connecting pad vias, the ground vias are simultaneously formed without requiring additional processing steps. This merging of operations resolves signal interference issues while avoiding increased fabrication costs.
Solution Approach 2:
The mask and litho-etching processes are designed to serve multiple functions: creating both connecting pad vias and ground vias in a single operation. This multi-functionality approach allows the fabrication process to address electrical coupling issues while maintaining cost efficiency by eliminating the need for dedicated ground via formation steps.
2Volume of moving object
If semiconductor chip package size is minimized, then device integration density increases, but electrical coupling between metal lines worsens
Solution Approach 1:
The patent implements local quality by strategically placing ground vias at specific locations around sensor devices and metal lines. These ground vias are positioned to provide localized shielding and reference potentials exactly where electrical coupling occurs, allowing miniaturization while maintaining signal integrity through targeted electromagnetic field management.
Solution Approach 2:
Ground vias serve as intermediary elements between signal-carrying metal lines and the ground plane. These intermediary structures provide controlled impedance paths and electromagnetic shielding, enabling close spacing of metal lines in miniaturized packages while preventing harmful electrical coupling through the mediating presence of ground references.
Data Source
AI summary
Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.