Stacked Chip Package With Hole Bottom Support Bulk
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Solution Overview
Problem
The existing chip packaging technologies face challenges in improving the reliability and structural stability of stacked chip packages, particularly in maintaining the structural integrity of conducting regions and preventing damage during the packaging process.
Innovation Solution
A chip package design that includes a first chip with a hole extending towards a second chip, a conducting layer connecting to a conducting or doped region, and a support bulk covering the bottom of the hole, which enhances structural strength and reliability by preventing damage to the conducting region during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hole is formed extending from the first chip towards the second chip to connect conducting layers, then electrical connection is achieved, but the structural strength and reliability of the conducting region deteriorate due to potential damage during bonding
Solution Approach 1:
A support bulk is formed at the bottom of the hole extending from the first chip towards the second chip. This support bulk serves as a cushioning structure that prevents damage to the conducting region during the bonding process, thereby maintaining both electrical connection reliability and conducting region structural strength simultaneously
2Reliability
If the support bulk completely covers the bottom of the hole, then the conducting region is fully protected from damage, but the manufacturing complexity increases
Solution Approach 1:
The support bulk is formed with a localized structure that covers the bottom of the hole. Rather than uniformly thickening the entire chip structure, the support bulk is precisely positioned only where needed at the hole bottom to protect the conducting region, achieving effective protection while minimizing additional manufacturing complexity
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.