Chip Package Structure With One-Step Hot-Press Bonding
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Solution Overview
Problem
The panel-level package (PLP) process is complex and costly, requiring multiple steps and higher production costs, which hinders the efficiency and cost-effectiveness of semiconductor chip packaging.
Innovation Solution
A packaging method that integrates the bonding and packaging of semiconductor chips into a single process step using a carrying board, a base structure, and an encapsulating material under hot pressing conditions, forming a metal-to-metal bond between chip connecting members and electrically connecting structures within the base structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If panel-level package (PLP) process is used to arrange and package multiple chips simultaneously, then production efficiency is improved, but process complexity and production costs increase
Solution Approach 1:
The patent merges the bonding process and packaging process into a single integrated step. The encapsulating material is applied to the carrying board with chips attached, and then both bonding and packaging occur simultaneously during one heating and pressing operation, eliminating the need for separate bonding and packaging process steps.
Solution Approach 2:
The encapsulating material serves multiple functions simultaneously: it acts as a bonding agent to attach chips to the substrate, provides packaging protection, and forms the final package structure. This multi-functional approach reduces the number of process steps needed while maintaining high production efficiency.
2Manufacturing precision
If multiple separate process steps are used for bonding and packaging, then manufacturing precision can be controlled, but processing time and production costs increase
Solution Approach 1:
The patent combines bonding and packaging into one simultaneous process step. The encapsulating material is heated and pressed in a single operation that achieves both chip bonding to the substrate and packaging encapsulation, reducing total processing time while maintaining precision through controlled heating and pressing parameters.
Solution Approach 2:
The encapsulating material is pre-applied to the carrying board before the simultaneous bonding and packaging step. This preliminary positioning ensures that when heating and pressing occur, the material is already in the correct position to bond chips and form the package structure in one operation.
3Reliability
If conventional packaging methods are used, then process steps are well-defined, but package size and production costs are larger and higher
Solution Approach 1:
The simultaneous bonding and packaging process allows the encapsulating material to directly bond chips to the substrate while forming the final package structure in one step, reducing the need for additional structural components and minimizing overall package size while maintaining reliability through the integrated process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces process steps, shortens processing time, miniaturizes package size, and increases package yield and reliability, meeting the requirements of high-end products and high performance.
Implementation Method 1
integrating the base structure, the chips, and the carrying board into a unitary structure under hot pressing conditions via an encapsulating material
Implementation Method 2
The at least one chip connecting member of each of the chips and the at least one electrically connecting structure in the corresponding one of the predetermined regions have a metal-to-metal bond formed therebetween and under the hot pressing conditions
Implementation Method 3
The encapsulating material is formed into an encapsulating layer under the hot pressing conditions, and the encapsulating layer is located between the carrying board and the base structure to isolate the chips from the external environment
Data Source
AI summary
A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.