Chip Scale Package Insulating Shell for Exposed Die Reliability
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Solution Overview
Problem
The existing wafer level chip scale package (WLCSP) technology exposes the surface of semiconductor chips, leading to potential damage and reduced reliability due to environmental factors such as stress, chemicals, and moisture.
Innovation Solution
A semiconductor package structure is developed, comprising a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and conductive structures. The protective insulating layer covers the RDL and the semiconductor die's surfaces, while conductive structures pass through the passivation layer to ensure electrical coupling, providing protection and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If WLCSP process is used to reduce chip size and form factor, then productivity and compactness are improved, but the chip surface becomes exposed to environment causing damage and reduced reliability
Solution Approach 1:
The patent applies a protective insulating layer (molding compound) that encapsulates the chip surface, RDL structure, and conductive structures. This thin film/shell approach protects the exposed chip surfaces from environmental damage while maintaining the compact WLCSP form factor and high productivity benefits.
2Volume of moving object
If chip size is reduced to make electronic products more compact, then volume and portability are improved, but the exposed surface area relative to volume increases making the chip more vulnerable to environmental damage
Solution Approach 1:
The protective insulating layer acts as a protective shell that encases the small chip, RDL structure, and conductive elements. This shell protection is particularly important for miniaturized devices where the surface-area-to-volume ratio is high, making the chip more susceptible to environmental factors like moisture and chemicals.
3Device complexity
If the chip surface is exposed after package separation to maintain simple structure, then device complexity is reduced, but the chip becomes vulnerable to stress, chemicals, and moisture
Solution Approach 1:
The protective insulating layer provides a simple yet effective encapsulation solution. The molding compound forms a continuous protective shell over the chip and RDL structure, preventing environmental exposure without adding complex multi-layer protection systems.
Data Source
AI summary
A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.