Chip-Package Insulation Extension for Leadframe Elimination
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Solution Overview
Problem
Current chip-package construction in semiconductor technology faces challenges such as x-y tolerances, leadframe deflection, bond line thickness issues, and high costs due to the need for large area copper carriers, which complicates the die attach process and module individualization.
Innovation Solution
A chip-package design that eliminates the need for leadframe carriers by using a chip-carrier with insulation material extending perpendicular to the chip lateral sides, allowing for electrical connections and individualization without sawing through a leadframe, thereby reducing material and processing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional leadframe carriers with large area copper are used, then electrical connections and mechanical support are provided, but manufacturing complexity and cost increase due to required sawing and etching processes
Solution Approach 1:
The patent extracts and eliminates the leadframe carrier from the package structure, replacing it with a substrate that integrates the chip carrier function. This removes the need for sawing through copper leadframes and performing etching operations, thereby reducing manufacturing complexity while maintaining electrical connection reliability through alternative means (substrate traces and bonding structures).
Solution Approach 2:
The patent merges the functions of the leadframe carrier and the package substrate into a single integrated substrate structure. This combination eliminates the need for separate leadframe components and complex assembly processes, reducing both manufacturing steps and overall device complexity while preserving all necessary electrical connection functions.
2Reliability
If large area copper carriers are used for chip embedding, then electrical connections are established, but material costs and processing costs increase
Solution Approach 1:
The patent extracts the large area copper leadframe from the package structure and replaces it with a substrate-based electrical connection system. This eliminates the need for extensive copper material while maintaining reliable electrical connections through substrate traces and bonding structures, thereby reducing both material quantity and associated costs.
Solution Approach 2:
The patent changes the electrical connection approach from using large area copper carriers to using substrate-integrated traces and bonding structures. This parameter change in the connection method reduces copper material consumption significantly while maintaining the necessary electrical connectivity for chip operation.
3Productivity
If sawing processes are used for module individualization through leadframe, then chips are separated into individual packages, but saw edges and impurities are introduced
Solution Approach 1:
The patent extracts and eliminates the leadframe carrier that requires sawing for module individualization. By using a substrate-based approach, the package can be individualized through simpler processes that do not involve sawing through copper leadframes, thereby preventing the introduction of saw edges and metallic impurities while maintaining productivity.
Data Source
AI summary
A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier.