Chip Package Insulating Layer for Leakage Reduction
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Solution Overview
Problem
Standard chip packaging technologies, such as quad flat no-lead (QFN) packages, are not suitable for small power devices as they may suffer from electrical leakage issues and have limited compatibility due to fixed leadframe arrangements and sizes, which can affect chip performance and packaging efficiency.
Innovation Solution
A chip packaging method involving the formation of bonding pins on a carrier, an insulating layer on the inactive chip face, electrical coupling of chip electrodes to these pins via conductive wires, and encapsulation, followed by peeling the carrier to expose the pins and insulating layer, ensuring insulation and compatibility without a pre-manufactured leadframe.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard chip packaging technologies (QFN packages) are used, then electrical connectivity is provided, but electrical leakage occurs and reliability deteriorates
Solution Approach 1:
An insulating layer is introduced as an intermediary between the chip inactive face and the carrier to prevent electrical leakage. This mediator layer electrically isolates the chip from the carrier while still allowing mechanical support and thermal management, thereby eliminating the harmful electrical leakage effect without compromising connectivity.
Solution Approach 2:
The packaging structure is segmented into distinct functional layers: the chip, the insulating layer, the carrier with bonding pins, and the encapsulant. This segmentation allows each component to perform its specific function independently, with the insulating layer specifically addressing the electrical leakage problem while other layers handle support, connectivity, and protection.
2Adaptability or versatility
If pre-manufactured leadframes with fixed arrangements are used, then electrical connectivity is achieved, but adaptability and compatibility are limited
Solution Approach 1:
The packaging method transitions from static, pre-fixed leadframe arrangements to a dynamic configuration where bonding pins are formed directly on the carrier in customizable patterns. This allows the electrical connectivity arrangement to be adapted to different chip designs and applications, significantly improving adaptability and compatibility while reducing the constraints of fixed leadframe geometries.
Solution Approach 2:
The carrier is prepared with bonding pins formed in advance at desired locations and patterns before chip mounting. This preliminary action enables flexible configuration of electrical connections tailored to specific chip requirements, allowing customization of pin arrangements to match different chip electrode layouts without being constrained by pre-manufactured leadframe designs.
3Reliability
If insulating materials are added to prevent leakage, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The insulating layer is merged with the carrier assembly to form an integrated structure. The insulating layer is applied directly to the carrier surface and serves multiple functions simultaneously: electrical isolation, mechanical support, and a bonding substrate for the chip. This merging eliminates the need for separate insulating components, thereby improving electrical isolation without significantly increasing overall device complexity.
Data Source
AI summary
A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.