Chip Package I/O Interface Voltage Level Shifting
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Solution Overview
Problem
Current chip packages face issues with voltage differences between interconnected dies leading to excessive self-heating, electromigration, and power leakage, as well as increased complexity and latency due to the need for dedicated I/O voltage supplies and voltage-level translators.
Innovation Solution
A chip package structure that allows independent voltage settings for each die, delivering power supplies only along the perimeter of the I/O attach region, enabling a single voltage-level translation and reducing the need for additional interconnects and voltage reference forwarding, thereby minimizing voltage differences and associated issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated I/O voltage supplies and voltage-level translators are used to connect dies with different voltage potentials, then reliable signal transmission is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the voltage-level translator component from the I/O interface by designing the receive I/O circuit to directly tolerate voltage differences between transmit and receive dies. This removal of the intermediate translation component simplifies the package structure while maintaining reliable signal transmission across voltage-domain boundaries.
Solution Approach 2:
The receive I/O circuit is designed with universal voltage tolerance, enabling it to directly receive signals from transmit dies operating at different voltage potentials without requiring dedicated voltage translation infrastructure. This multi-functional capability allows the same circuit to operate across multiple voltage domains.
2Reliability
If voltage-level translators and regulators are implemented to manage voltage differences between dies, then signal integrity is maintained, but power consumption increases
Solution Approach 1:
The patent removes voltage-level translators and regulators from the signal path by designing the receive I/O circuit to natively tolerate voltage differences. This elimination of active translation components directly reduces power consumption while preserving signal integrity through direct voltage-domain compatibility.
3Device complexity
If I/O circuits are designed to tolerate voltage differences without translation, then device complexity is reduced, but signal transmission reliability may deteriorate
Solution Approach 1:
The patent changes the voltage tolerance parameters of the receive I/O circuit to accommodate a broader range of input voltage potentials. By adjusting the circuit's operating parameters to tolerate voltage differences directly, the design achieves simplified architecture without compromising signal transmission reliability.
4Ease of manufacture
If perimeter-only power delivery is used for I/O attach region, then manufacturing complexity is reduced, but power delivery capability may be limited
Solution Approach 1:
The patent segments the power delivery infrastructure to provide dedicated power supplies for the I/O attach region perimeter, separating it from the main die power distribution. This segmentation simplifies manufacturing by creating distinct power zones while maintaining adequate power delivery capability through targeted perimeter供电 to the I/O circuits.
Data Source
AI summary
An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.