Chip Package Structure With Laser Lift-Off and Flush Metal Vias
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Solution Overview
Problem
The Fan-Out Wafer Level Packaging (FOWLP) technology for integrated circuits has low efficiency and high costs, necessitating an improved chip packaging method that enhances efficiency and reduces costs while maintaining reliability and yield.
Innovation Solution
A chip package method involving a transparent substrate coated with an organic polymer material layer, followed by a protective layer, alignment parts, and encapsulating layers, with metal parts formed to connect chips electrically, and laser irradiation to lift off the substrate, simplifying the packaging process and improving alignment accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If FOWLP technology is used for chip packaging, then integration level and volume miniaturization are achieved, but manufacturing efficiency decreases and cost increases
Solution Approach 1:
The packaging process is divided into distinct stages: substrate preparation with organic polymer coating, chip attachment on the protective layer, encapsulating layer formation, and final laser lift-off. This segmentation allows each stage to be optimized independently, improving overall manufacturing efficiency while achieving miniaturization
Solution Approach 2:
The organic polymer material layer is coated on the transparent substrate before chip attachment, and the protective layer is deposited in advance. These preliminary actions prepare the substrate structure beforehand, enabling more efficient chip packaging operations and reducing overall process time
2Adaptability or versatility
If FOWLP technology is used for chip packaging, then integration level is improved, but manufacturing cost increases
Solution Approach 1:
The transparent substrate serves multiple functions: it provides mechanical support, allows laser irradiation for lift-off, and enables alignment for chip attachment. The organic polymer layer and protective layer work together for both structural integrity and process facilitation. This multi-functionality reduces the need for additional components, lowering manufacturing cost while maintaining high integration level
Solution Approach 2:
The traditional mechanical substrate removal is replaced by laser irradiation that exploits the organic polymer's absorption characteristics. This substitution enables precise, contactless lift-off of the substrate after packaging, improving ease of manufacture and reducing costs associated with mechanical removal methods
3Manufacturing precision
If alignment parts are formed on the protective layer, then alignment accuracy is improved, but process complexity increases
Solution Approach 1:
The protective layer serves as an intermediary between the organic polymer material layer and the alignment parts. It provides a suitable surface for forming alignment parts while protecting the underlying organic polymer structure. This intermediary approach enables precise alignment without directly modifying the organic polymer layer, maintaining process simplicity while achieving high alignment accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the efficiency and reliability of chip packaging by simplifying the process, improving alignment accuracy, and reducing costs, while preventing external matter ingress and maintaining chip performance, thus addressing the inefficiencies and high costs of FOWLP.
Implementation Method 1
irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate
Implementation Method 2
irradiating the second side of the transparent substrate by a laser to lift off the transparent substrate
Data Source
AI summary
Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.