Chip Package Laser Stopper for Flat Sensor Surface
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Solution Overview
Problem
The manufacturing of fingerprint or RF sensors is hindered by the need for a flat sensing surface, and existing processes like chemical vapor deposition and patterning are time-consuming and costly, affecting detection accuracy.
Innovation Solution
A chip package design that includes a chip with a conductive pad, a laser stopper, an isolation layer, a redistribution layer, and an insulating layer, where the laser stopper shields the laser to form a second through hole, allowing for electroplating of the redistribution layer without the need for CVD and patterning processes, thereby improving flatness and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical vapor deposition and patterning processes are used to form isolation layer and redistribution layer, then electrical connection to conductive pad is achieved, but process time increases and equipment cost increases
Solution Approach 1:
The patent extracts and eliminates the CVD and patterning processes from the manufacturing flow. Instead of using complex multi-step processes, it directly forms through-holes through the substrate to expose conductive pads, achieving electrical connection through simpler drilling and plating operations, thereby reducing process time while maintaining connection reliability
Solution Approach 2:
The patent inverts the conventional approach by first forming through-holes to expose conductive pads, then building up isolation and redistribution layers around these exposed pads. This reverse sequence eliminates the need for preliminary CVD isolation layer formation and complex patterning, streamlining the manufacturing process
2Reliability
If chemical vapor deposition and patterning processes are used to form isolation layer and redistribution layer, then electrical connection to conductive pad is achieved, but equipment cost increases
Solution Approach 1:
The patent removes the requirement for expensive CVD equipment and photolithography patterning equipment. By using direct drilling or laser drilling to form through-holes followed by simple electroplating for redistribution layers, the invention achieves electrical connections using less costly manufacturing equipment
Solution Approach 2:
The patent employs simpler, more disposable-like processes such as direct drilling and electroplating instead of expensive, complex CVD and patterning equipment. These simpler processes can be performed with less costly equipment that doesn't require the same level of precision and maintenance as CVD systems
3Reliability
If additional processes are performed on first surface of chip, then electrical connection is achieved, but flatness of chip surface deteriorates
Solution Approach 1:
The patent segments the manufacturing processes by performing all necessary operations for electrical connection on the second surface of the chip, leaving the first surface untouched. This spatial segmentation ensures that the sensing surface flatness is preserved while still achieving the required electrical connections through separate processing on the opposite surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces process time and equipment costs, maintains the flatness of the chip surface, and enhances detection accuracy by omitting CVD and patterning processes, while enabling electrical connection to the conductive pad.
Implementation Method 1
a laser is used for penetrating the isolation layer and the conductive pad and forming a second though hole
Implementation Method 2
a redistribution layer is electroplated on the third surface of the isolation layer, a sidewall of the second though hole, and the laser stopper that is in the second though hole
Data Source
AI summary
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.