Chip Package Structure With Conductive Pillars for Low-Warpage Joints
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving efficient integration density, reducing package size, and improving reliability of joints while maintaining heat dissipation and operational performance.
Innovation Solution
The process involves forming a chip package structure by bonding chips to a substrate and redistribution structure using conductive bumps and pillars, with an underfill layer and molding layer to enhance mechanical support and electrical connectivity, and adjusting material thicknesses to reduce warpage and improve joint reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are bonded to substrate and redistribution structure using conductive bumps and pillars, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the electrical connection path into distinct functional elements: conductive bumps on the chip, underfill layer for mechanical support, substrate with through-holes, and redistribution structure with conductive pillars. This segmentation allows each component to be optimized independently while maintaining overall reliability.
Solution Approach 2:
The underfill layer acts as an intermediary between the chip and substrate, providing mechanical support and stress relief. The molding compound serves as an intermediary encapsulating the entire assembly, protecting it while allowing thermal expansion. These intermediary elements reduce manufacturing complexity by decoupling the requirements of different components.
2Stability of the object's composition
If material thicknesses are adjusted to reduce warpage, then structural stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent systematically varies material thickness parameters (substrate thickness, molding compound thickness, underfill layer thickness) to achieve optimal warpage control. By changing these parameters within specified ranges, the structure maintains stability without requiring extreme manufacturing precision.
Solution Approach 2:
The patent uses composite material structures with different thermal and mechanical properties: the substrate (e.g., PCB or ceramic), molding compound (epoxy-based), and underfill layer (adhesive material). The composite nature allows compensation for warpage through material selection rather than precise thickness control alone.
3Productivity
If integration density is enhanced and package size is reduced, then operational speed is improved, but heat dissipation challenges increase
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat management by using vertical conductive pillars extending through the substrate, and by incorporating thermal vias in the redistribution structure. This dimensional change allows heat to escape in multiple directions, addressing thermal challenges in compact high-density packages.
4Reliability
If conductive pillars extend through molding layer and substrate, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The conductive pillars are formed in the substrate before the molding compound is applied, and the through-holes are prepared in advance. This preliminary action allows the complex structural elements to be in place before final encapsulation, simplifying the overall manufacturing sequence while maintaining connectivity reliability.
Data Source
AI summary
A method for forming a chip package structure is provided. The method includes forming a conductive pillar in a substrate layer, forming a recess in the substrate layer, disposing a chip in the recess, forming a molding layer in the recess and surrounding the chip. and forming a redistribution structure over the substrate layer and electrically connecting the conductive pillar to the chip.