Chip Package Protective Layer for Thick Metal Dicing

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Solution Overview

Problem

The cutting of chip packages with thick metal layers leads to tool damage and chipping of edges, affecting the quality and yield of the packages.

Innovation Solution

A chip package design that includes an insulating protective layer around the thick metal layer, allowing cutting tools to only cut the protective layer instead of the metal, thereby protecting the metal during the cutting process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cutting tools are used to cut through thick metal layers in chip packages, then the chip packages can be separated into individual units, but the cutting tools are easily damaged and edge chipping occurs

Engineering Contradiction:
Improvechip package separation efficiencyVSAvoidcutting tool durability and edge quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The invention segments the wafer structure by introducing grooves between adjacent rectangular chips that extend through the thick metal layer to the front surface. This segmentation allows cutting tools to follow predefined paths through the grooves rather than cutting through solid metal, reducing tool damage and edge chipping while maintaining production efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The grooves are formed in advance before the cutting process, creating predetermined cutting paths through the thick metal layer. This preliminary action eliminates the need for tools to forcibly cut through metal during the separation process, thereby preventing tool damage and edge chipping while maintaining high productivity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12568847B2Chip package and method of manufacturing the same
Publication Date: 2026.03.03 WALTON ADVANCED ENG INC
  • US12568847B2 patent drawing
  • US12568847B2 patent drawing
  • US12568847B2 patent drawing

AI summary

A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.