Chip Package Metal Shielding for EMI and Light Interference

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Solution Overview

Problem

Chip packages in electronics face issues with electromagnetic interference (EMI) and light interference, leading to reduced reliability and functionality.

Innovation Solution

A chip package design incorporating a metal shielding layer, a redistribution layer (RDL), and a method of manufacturing that includes a conductive circuit and a metal shielding layer made of silver adhesive, with a bottom protective layer of nickel or gold, to protect the chip and improve structural strength.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal shielding layer is added to protect the chip from electromagnetic interference and light interference, then the reliability of the chip package is improved, but the device complexity increases

Engineering Contradiction:

Improvechip package reliabilityVSAvoidpackage structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the shielding function with the existing package structure by integrating the metal shielding layer into the substrate or housing design. This merging approach allows the shielding function to be added without creating a completely separate component system, thereby improving reliability while minimizing the increase in device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal shielding layer serves multiple functions simultaneously: it provides electromagnetic interference shielding, light interference protection, and structural support for the chip package. This multi-functionality approach allows a single component to address multiple protection needs, improving reliability without proportionally increasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a metal shielding layer is added to protect the chip, then the reliability is improved, but the manufacturing process becomes more complex

Engineering Contradiction:

Improvechip package reliabilityVSAvoidmanufacturing process ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The metal shielding layer is designed to be formed or attached to the substrate before the chip mounting process. This preliminary action allows the shielding structure to be prepared in advance as part of the substrate fabrication, integrating it into the existing manufacturing flow and minimizing additional manufacturing complexity while ensuring reliability.

Inventive Principle:

Principle #10Preliminary action

3Object-affected harmful factors

If the metal shielding layer covers the second surface of the chip, then protection from interference is improved, but the weight of the chip package increases

Engineering Contradiction:

Improveelectromagnetic and light interference protectionVSAvoidchip package weight

Core Design Contradiction:

Object-affected harmful factorsVSWeight of stationary object

Solution Approach 1:

The metal shielding layer is applied selectively to the second surface of the chip where interference protection is most needed, rather than covering the entire chip package uniformly. This local quality approach provides targeted protection against electromagnetic and light interference while minimizing the overall weight increase by limiting the metal material to only the necessary areas.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively shields the chip from external electromagnetic and light interference, enhancing the structural strength and reliability of the chip package while ensuring electrical connectivity.

Implementation Method 1

The metal shielding layer is covering the second surface of the chip and used not only for protecting the chip and the conductive circuit from external electromagnetic interference or light interference

Methodology Applied

Scientific EffectElectromagnetic shielding: Faraday Cage

Implementation Method 2

Methodology Applied

Scientific EffectLight blocking: Absorption (EM radiation)

Implementation Method 3

The RDL is disposed on a surface of the chip protective layer of the chip and provided with at least one conductive circuit for electrical connection with the die pad of the chip

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 4

the back surface of the metal shielding layer is provided with a bottom protective layer... The bottom protective layer is further made of metal material such as nickel (Ni) or gold (Au)

Methodology Applied

Scientific EffectOxidation resistance: Oxidation

Data Source

PatentUS20240162164A1Chip package with metal shielding layer and method of manufacturing the same

Publication Date: 2024.05.16 WALTON ADVANCED ENG INC

AI summary

A chip package with a metal shielding layer and a method of manufacturing the same are provided. The chip package includes a chip, a redistribution layer (RDL), and a metal shielding layer. The chip is composed of a first surface and a second surface and cut from a wafer. The RDL is disposed on a surface of at least one chip protective layer of the chip and provided with at least one conductive circuit for electrical connection with the die pad of the chip. The conductive circuit includes at least one pad which is exposed on a surface of the RDL for electrical connection with the outside. The metal shielding layer is covering the second surface of the chip not only for protecting the chip and the conductive circuit from external electromagnetic interference or light interference but also for increasing structural strength of the chip package.