Chip Package With Nested Via For High-Density Routing
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Solution Overview
Problem
Current chip packages face challenges in achieving high-density conducting routes and structural reliability as chip sizes shrink, necessitating improved through-substrate via technologies.
Innovation Solution
A chip package design featuring a substrate with conducting pads, a dielectric layer, and a conducting layer within a hole extending from the upper to the lower surface, electrically connecting to the pads, enhancing structural reliability and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If chip size continues to shrink to accommodate miniaturization, then device portability and integration density improve, but achieving high-density conducting routes and maintaining structural reliability become more difficult
Solution Approach 1:
The conducting pad structure is segmented into multiple layers (first conducting pad layer, second conducting pad layer, third conducting pad layer) with dielectric layers in between. This segmentation allows the via structure to connect to multiple discrete conducting pads at different levels, distributing the mechanical and electrical stress across multiple interfaces rather than a single contact point, thereby improving structural reliability in miniaturized chips.
Solution Approach 2:
The via structure is designed to nest through multiple conducting pad layers and dielectric layers simultaneously. The via hole penetrates through the substrate and exposes portions of multiple conducting pads at different depths, creating a nested configuration where the via connects to conducting pads at various levels within the stacked structure, enabling high-density routing while maintaining reliability.
2Adaptability or versatility
If the number of conducting routes needs to be increased for multi-functionality, then chip functionality improves, but the complexity of forming individual vias for each route increases
Solution Approach 1:
Multiple conducting pad layers are merged into a single stacked structure within the substrate. A single via hole can expose and connect to multiple conducting pads from different layers simultaneously, combining multiple potential connection points into one unified via structure. This merging approach allows multiple conducting routes to be achieved through a simplified single via formation process rather than requiring separate via holes for each connection.
Solution Approach 2:
The conducting pad structure transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration with multiple layers at different vertical levels. This dimensional change allows via holes to access conducting pads at different depths through the substrate, enabling multiple conducting routes to be established through a single via formation process by exploiting the vertical dimension rather than requiring multiple lateral via holes.
Data Source
AI summary
According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.