Chip Package Multi-Mask Wiring Layout for Overlay Tolerance
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Solution Overview
Problem
The semiconductor industry faces challenges in simplifying the fabrication process and reducing costs for integrated fan-out packages, which are crucial for heterogeneous integration and future packaging solutions due to complex manufacturing processes and high costs.
Innovation Solution
The process involves forming conductive pillars on a wafer, creating a redistribution circuit structure with multiple inter-dielectric and conductive layers, and using a multi-mask process for patterning to enhance adhesion and reduce equivalent series resistance and inductance, while also incorporating a protection layer to prevent damage during dicing and encapsulating conductive pillars to ensure reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fabrication processes are used for integrated fan-out packages, then manufacturing precision and reliability can be maintained, but the fabrication process becomes complex and costs increase
Solution Approach 1:
The fabrication process is divided into distinct stages: forming conductive pillars on the wafer, creating the redistribution circuit structure with multiple layers, and applying protection layers. Each stage is independently optimized, allowing complex packaging to be achieved through manageable sequential steps rather than a monolithic complex process
Solution Approach 2:
Conductive pillars are formed on the wafer before dicing, and protection layers are applied in advance to prevent damage during subsequent processing. These preliminary actions ensure reliability is built into the structure before critical operations like dicing occur, avoiding the need for complex post-processing repairs
2Reliability
If traditional fabrication processes are used for integrated fan-out packages, then manufacturing precision and reliability can be maintained, but fabrication costs increase
Solution Approach 1:
Multiple functions are combined into integrated structures: the redistribution circuit structure performs both electrical redistribution and mechanical support, while conductive pillars provide both electrical connection and structural integrity. This merging reduces the number of separate components and assembly steps, lowering fabrication costs while maintaining reliability
Solution Approach 2:
The patent optimizes parameters such as the dimensions and material composition of conductive pillars and inter-dielectric layers to achieve the desired electrical performance (reduced equivalent series resistance and inductance) at lower fabrication costs. By carefully controlling these parameters, high reliability is achieved without requiring expensive advanced manufacturing processes
3Reliability
If conductive pillars are formed with multiple inter-dielectric and conductive layers, then adhesion and electrical characteristics are improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent employs composite structures with multiple inter-dielectric and conductive layers, where each layer is optimized for its specific function. The conductive pillars are surrounded by multiple layers that provide both electrical connectivity and mechanical adhesion, creating a composite structure that achieves superior electrical characteristics (reduced equivalent series resistance and inductance) while the systematic layering approach keeps the fabrication process manageable
Data Source
AI summary
A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.