Chip Package Conductive Pad Protection During Cutting
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Solution Overview
Problem
Conductive pads in chip packages are damaged during the cutting process, leading to reduced reliability and poor electrical properties due to chipping and scratching.
Innovation Solution
A chip package design featuring a semiconductor substrate with conductive pads protected by a chip passivation layer and an insulating protective layer, where the packaging layer is used as a hard mask to expose the pads without additional photolithography, preventing damage during cutting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cutter is used to form openings between chips during the cutting process, then chip separation is achieved, but conductive pads are damaged and scratched by chippings
Solution Approach 1:
The patent applies preliminary action by forming the insulating protective layer over the conductive pads before the cutting process. This protective layer is prepared in advance to prevent damage during subsequent cutting operations, rather than attempting to protect the pads during or after damage occurs.
Solution Approach 2:
The insulating protective layer serves as an intermediary element between the cutter and the conductive pads. It acts as a mediator that allows the cutting process to proceed while preventing direct contact between the cutter-induced chippings and the conductive pads, thus protecting the pads without interfering with chip separation.
2Reliability
If additional photolithography steps are used to protect conductive pads, then pad damage is prevented, but manufacturing complexity and process time increase
Solution Approach 1:
The patent merges the protective function with the existing packaging layer structure. The insulating protective layer is integrated into the packaging layer system, combining the functions of protection and packaging structure in a single integrated solution, eliminating the need for separate photolithography protection steps.
Solution Approach 2:
The packaging layer is designed to serve multiple functions: it provides mechanical protection, electrical insulation, and structural support, while also incorporating the insulating protective layer function. This multi-functionality eliminates the need for dedicated photolithography steps solely for pad protection.
3Ease of operation
If the packaging layer is patterned to expose conductive pads, then wire bonding access is enabled, but risk of pad damage during patterning increases
Solution Approach 1:
The insulating protective layer is formed in advance before the packaging layer patterning step. This preliminary protection ensures that when the packaging layer is later patterned to expose pads for wire bonding, the conductive pads are already protected from damage during the patterning process.
Solution Approach 2:
The insulating protective layer acts as a cushioning protection layer prepared beforehand. It absorbs or prevents the harmful effects of the patterning process on the conductive pads, providing a buffer that protects the pads while still allowing necessary access for wire bonding.
Data Source
AI summary
A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.