Chip Package Substrate Pad Structure for Solder Adhesion
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Solution Overview
Problem
Conventional chip package structures with solder-mask-defined pads experience reliability issues due to unstable solder ball adhesion and varying fabrication processes required for different substrates, leading to potential static damage and connectivity problems.
Innovation Solution
A package substrate design featuring a laminated layer with patterned conductive and solder-mask layers, including outer pads connected to inner pads exposed through openings, and a padding pattern that elevates above the outer pads, preventing contact with carriers or electronic components and enhancing electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pad is of a solder-mask-defined (SMD) type with openings exposing portions of the pad, then the solder-mask layer can be precisely formed, but the solder ball contact area is reduced leading to unstable adhesion
Solution Approach 1:
The pad structure is segmented into multiple components: the inner pad exposed through the opening, the outer pad extending beyond the opening, and the padding pattern surrounding the opening. This segmentation allows the solder ball to contact multiple pad regions simultaneously, increasing the total contact area and improving adhesion stability while maintaining precise solder-mask formation.
Solution Approach 2:
The pad structure extends in multiple dimensions: the outer pad expands the contact area in the planar dimension beyond the opening, while the padding pattern adds vertical dimension with its raised profile. This multi-dimensional expansion ensures adequate solder ball contact area without compromising solder-mask precision.
2Ease of manufacture
If the package substrate is disposed directly on the carrier with pads contacting the carrier, then the assembly process is simple, but static damage may occur to the pads or chip
Solution Approach 1:
The padding pattern acts as an intermediary element between the package substrate and the carrier. With its raised profile exceeding the outer pad height, it serves as the primary contact point with the carrier, preventing direct contact between the pads/carrier and eliminating static damage risks, while maintaining assembly simplicity.
Solution Approach 2:
The padding pattern provides beforehand cushioning by being positioned to contact the carrier first during assembly. Its elevated structure creates a protective buffer that prevents harmful static discharge from reaching the sensitive pad and chip structures.
3Object-affected harmful factors
If the outer pad height is increased to prevent carrier contact, then static damage is prevented, but solder ball connection to external components is affected
Solution Approach 1:
Different regions of the pad structure have different heights tailored to their specific functions: the padding pattern has the greatest height for carrier contact and static protection, the outer pad has intermediate height for solder ball connection, and the inner pad has the lowest height for electrical connection. This localized height differentiation resolves the contradiction between static protection and solder connection reliability.
Data Source
AI summary
A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.