Integrated Chip Package Passive Elements Circuit Layer
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Solution Overview
Problem
Existing chip package structures are inefficient in operational effectiveness due to the separate placement of passive elements on carriers, which increases product volume and cost without enhancing streamlined electronic product functionality.
Innovation Solution
A chip package structure is developed where a circuit layer with bumps and passive element electrodes, made of the same material, is formed on the chip's surface, with passive element material placed between the electrodes to create a passive element, allowing for electrical connection through bumps to a substrate, thereby integrating passive elements directly on the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive elements are separately placed on carriers through wiring bonding or bumps bonding, then electrical connection is achieved, but the usage area of the carrier increases and the overall cost increases
Solution Approach 1:
The patent merges the passive elements directly onto the chip surface, integrating them with the circuit layer. The passive elements share the same substrate (chip) as the active circuit, eliminating the need for separate carrier placement and wiring bonding. This integration reduces the overall usage area while maintaining electrical connection functionality through shared bumps and circuit traces.
2Reliability
If passive elements are separately placed on carriers through welding, then electrical connection is achieved, but the overall cost increases and electronic product volume increases
Solution Approach 1:
The patent combines the formation of passive elements and active circuits into a single integrated structure on the chip. Both are formed using the same manufacturing processes (plating, coating) on the same substrate, eliminating separate welding operations and reducing manufacturing complexity and cost.
Solution Approach 2:
The chip substrate serves multiple functions: it acts as both the active circuit substrate and the passive element substrate. The bumps serve dual purposes for both active and passive elements, providing universal electrical connection points that reduce the need for additional connection structures and降低制造成本.
3Reliability
If passive elements are disposed on the carrier, then electrical connection is achieved, but it is not conducive to streamlined electronic product volume
Solution Approach 1:
The patent merges passive elements and active circuits into a single integrated chip structure, eliminating the need for separate carrier mounting. This integration significantly reduces the overall package volume as all components are consolidated within the chip footprint rather than requiring additional carrier space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances operational effectiveness by integrating passive elements on the chip, reducing volume and cost while improving signal transmission and circuit density.
Implementation Method 1
The bumps and the passive element electrodes of the circuit layer are formed through a plating process in the same step on the surface of the chip
Implementation Method 2
coating a passive element material between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element
Data Source
AI summary
A chip package structure including a chip, a circuit layer, a passive element material and a substrate is provided. The circuit layer is disposed on a surface of the chip, wherein the circuit layer includes a plurality of bumps and a plurality of passive element electrodes. The bumps and the passive element electrodes have the same material, and the passive element electrodes are electrically connected with part of the bumps. The passive element material is disposed between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element located on the surface of the chip. The chip is disposed on the substrate and faces the substrate by the surface, so that the chip and the passive element are electrically connected to the substrate through the bumps. A method of manufacturing the chip package structure aforementioned is also provided.