Chip-Scale Package Pillar Structure for Low-Diffusion I/O Reliability
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Solution Overview
Problem
Microelectronic devices face challenges in meeting reliability and cost targets due to increased power and current density through I/O structures, leading to higher temperatures and electromigration risks as they shrink in size.
Innovation Solution
A microelectronic device design featuring dielectric layers and pillars with conductive columns and heads that extend laterally, supported by a dielectric layer, which are formed using various fabrication methods to enhance structural integrity and reduce copper diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the size of microelectronic devices is reduced to meet cost targets, then device cost is reduced, but power and current density through I/O structures increases leading to higher temperatures and electromigration risks
Solution Approach 1:
The I/O structure is segmented into multiple components: a base layer, an intermediate layer with through-holes, and a top layer. This segmentation allows current to be distributed through multiple pathways rather than concentrated in a single structure, reducing current density and electromigration risk while maintaining the reduced device size for cost effectiveness.
Solution Approach 2:
The patent introduces a vertical dimension by creating through-holes that extend through the intermediate layer, transforming a planar I/O structure into a three-dimensional architecture. This dimensional change provides additional current pathways and散热 channels, reducing both current density and temperature while maintaining small footprint.
2Power
If power and current density are increased through I/O structures, then device functionality is enhanced, but temperatures increase and reliability decreases
Solution Approach 1:
The intermediate layer is selectively positioned beneath high-power I/O regions rather than uniformly across the entire device. This local quality approach concentrates thermal management resources where power density is highest, effectively reducing temperatures at critical locations without adding unnecessary structure elsewhere.
Solution Approach 2:
The intermediate layer acts as an intermediary thermal management structure between the base layer and top layer. It provides through-holes that serve as thermal pathways, mediating heat transfer from high-power regions to lower temperature zones, thereby reducing temperature-related failures while maintaining enhanced power capability.
3Ease of manufacture
If conventional packaging methods are used, then fabrication is simpler, but copper diffusion occurs and structural integrity is compromised
Solution Approach 1:
The intermediate layer with through-holes is formed before final assembly and bonding operations. This preliminary action establishes copper-containing structures in their final positions early in the fabrication process, allowing subsequent steps to proceed without risk of copper diffusion compromising structural integrity, while maintaining relatively simple overall fabrication.
Data Source
AI summary
A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.