Electronic Chip Package Reduced Contact Pad Pitch via Multi-Layer Vias
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Solution Overview
Problem
Semiconductor devices with tight contact pad pitches face reliability issues due to shorts between cover pads, limiting the minimum achievable contact pad pitch to around 70 microns, which is undesirable for further miniaturization.
Innovation Solution
The solution involves forming multi-layer vias through cover pads positioned along a dielectric boundary, allowing the vias to extend through both dielectric layers to contact pads, thereby minimizing the contact pad pitch without the need for intervening pads and reducing alignment tolerances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the contact pad pitch is reduced to increase device complexity and I/O connections, then the number of contact pads increases, but shorts occur between cover pads associated with adjacent contact pads
Solution Approach 1:
The patent introduces a vertical stacking dimension by forming vias through multiple dielectric layers to reach contact pads. This multi-layer via structure allows cover pads to be positioned in different vertical planes, providing an additional spatial dimension for electrical isolation. The via structure extends through first and second dielectric layers, with cover pads formed at different heights, thereby preventing shorts between adjacent contact pads while maintaining reduced pitch.
Solution Approach 2:
The patent introduces intermediate dielectric layers between adjacent contact pads and their associated cover pads. These dielectric layers act as insulating barriers that prevent electrical shorts while allowing the vias to pass through. The intermediate dielectric structure mediates the spatial relationship between adjacent pads, enabling reduced pitch while maintaining reliability.
2Reliability
If the minimum contact pad pitch is increased to 70 microns to ensure reliability with traditional via structures, then electrical isolation is improved, but device miniaturization is constrained
Solution Approach 1:
The patent transitions from a planar via structure to a multi-layer vertical via structure. By extending vias through multiple dielectric layers and positioning cover pads at different vertical heights, the invention utilizes the vertical dimension to achieve electrical isolation. This allows the horizontal pitch between contact pads to be reduced below the traditional 70-micron limit while maintaining reliability through the added vertical separation.
3Length of moving object
If multi-layer vias are formed through cover pads positioned along a dielectric boundary, then contact pad pitch is minimized below the traditional limit, but manufacturing complexity increases
Solution Approach 1:
The patent segments the via structure into multiple layers, with each via passing through specific dielectric layers and forming connections at different vertical levels. This segmentation allows for reduced pitch by distributing the electrical isolation function across multiple layers, but increases manufacturing complexity due to the need for precise alignment and formation of each via layer.
Data Source
AI summary
An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.