Chip Package Assembly with Planar Inner Leads for Miniaturization
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Solution Overview
Problem
Traditional chip packaging methods face challenges in miniaturization, lightweight design, and multi-functionality due to large package size and thickness, as well as high parasitic resistance from wire bonding, which affects package quality and efficiency.
Innovation Solution
A chip package assembly featuring a first and second substrate with inner leads, a plastic package, and outer leads that expose inner leads on the sides to reduce size and thickness, and improve thermal dissipation and reliability by directly connecting chip electrodes to external circuitry through inner and outer leads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect chip electrodes to leads, then electrical connection is achieved, but package height increases and parasitic resistance increases
Solution Approach 1:
The patent transitions from traditional wire bonding (three-dimensional space occupation) to a planar lead frame structure where leads are arranged on the same plane as the chip electrodes. This dimensional reorganization eliminates the need for vertical wire bonds, reducing package height while maintaining electrical connectivity through direct planar contact between chip electrodes and lead frame pads.
Solution Approach 2:
The invention extracts and eliminates the wire bonding component from the packaging structure. By removing the wire bonds and their associated vertical routing, the design achieves direct electrical connection between chip electrodes and lead frame leads, thereby reducing package height and eliminating the parasitic resistance introduced by wire bonds.
2Reliability
If wire bonding is used to connect chip electrodes to leads, then electrical connection is achieved, but parasitic resistance increases
Solution Approach 1:
The invention extracts and eliminates the wire bonding component from the packaging structure. By removing the wire bonds and their associated vertical routing, the design achieves direct electrical connection between chip electrodes and lead frame leads, thereby reducing package height and eliminating the parasitic resistance introduced by wire bonds.
Solution Approach 2:
The patent merges the chip electrode connection directly with the lead frame structure, eliminating the intermediate wire bond layer. The chip electrodes are positioned to make direct contact with lead frame pads, creating a unified low-resistance electrical path that combines the chip and lead frame into a more integrated structure.
3Reliability
If traditional chip packaging is used, then chip electrodes can be connected to external circuitry, but package size and thickness increase
Solution Approach 1:
The patent transitions from traditional wire bonding (three-dimensional space occupation) to a planar lead frame structure where leads are arranged on the same plane as the chip electrodes. This dimensional reorganization eliminates the need for vertical wire bonds, reducing package height while maintaining electrical connectivity through direct planar contact between chip electrodes and lead frame pads.
Solution Approach 2:
Instead of routing connections vertically through wire bonds above the chip, the invention inverts the approach by arranging leads in the same plane as the chip electrodes and making direct horizontal contact. This inverted routing strategy reduces the vertical dimension and overall package volume.
Data Source
AI summary
In one embodiment, a chip package assembly can include: a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to the first surface, where the second surface is provided with a first group of inner leads; at least one chip layer above the first group of inner leads, where each of the chip layers comprises a third surface and a fourth surface opposite to the third surface, where electrodes on the third surface that that lie at the lowest level are electrically coupled to the first group of inner leads through a first connector; and a second substrate above the fourth surface on the topmost layer and having a fifth surface, and where the fifth surface is provided with a second group of inner leads electrically coupled to the electrodes on the fourth surface on the topmost layer.