Fan-Out Chip Package Planarization for Fine-Pitch Redistribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density and smaller feature sizes in redistribution circuit structures within integrated fan-out packages, while maintaining a large process window and reducing minimum feature size.
Innovation Solution
The formation of a redistribution structure involves a multi-layered approach with dielectric and conductive features, where a high degree of planarization is achieved through partial removal and planarization processes, allowing for the formation of fine pitch redistribution layers with increased process window and reduced critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the minimum feature size of the redistribution circuit structure is reduced to achieve higher integration density, then the integration density improves, but the process window decreases
Solution Approach 1:
A planarization layer is formed beforehand to flatten the surface of the encapsulant before forming the redistribution circuit structure. This preliminary planarization action creates a uniform baseline surface that allows subsequent fine-pitch features to be formed with better control, thereby reducing minimum feature size while maintaining an acceptable process window
Solution Approach 2:
The patent applies planarization specifically to the surface region of the encapsulant where the redistribution circuit structure will be formed. This localized planarization improves the surface quality in the critical area without requiring planarization of the entire structure, enabling better control over minimum feature size in the redistribution layer
2Manufacturing precision
If the minimum feature size of the redistribution circuit structure is reduced to achieve higher integration density, then the integration density improves, but the yield rate decreases
Solution Approach 1:
The planarization layer is formed in advance to create a flat surface foundation before depositing the redistribution circuit structure. This preliminary action reduces surface variability and defect formation during subsequent processing steps, enabling smaller feature sizes to be achieved with higher yield rates
Solution Approach 2:
The planarization layer acts as an intermediary between the encapsulant surface and the redistribution circuit structure. This intermediate layer absorbs surface irregularities and provides a uniform platform for forming fine-pitch features, thereby improving both the achievable minimum feature size and the yield rate
3Manufacturing precision
If a fine pitch redistribution layer is formed directly on the encapsulant surface, then the critical dimensions can be reduced, but the process window decreases due to surface non-planarity
Solution Approach 1:
The planarization layer is deposited beforehand to flatten the encapsulant surface before forming the fine-pitch redistribution layer. This preliminary planarization action eliminates surface non-planarity issues that would otherwise constrain the process window, allowing critical dimensions to be reduced while maintaining process robustness
Solution Approach 2:
The planarization layer serves as a temporary, sacrificial structure that is formed specifically to provide surface planarity during the critical deposition phase. After serving its planarization function, this layer can be selectively removed or integrated into the final structure, having fulfilled its purpose of enabling fine-pitch feature formation
Data Source
AI summary
A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.