Chip Package Pad Layout for Shorter Power Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Common chip packaging technologies using wire-bonding result in longer power paths with high parasitic resistance, leading to IR drops and reduced power integrity, especially in larger chips.
Innovation Solution
An electronic package structure with a chip design featuring a first common pad in the peripheral region, an internal bonding wire connecting this pad to an individual core pad, and external bonding wires, which collectively enhance power integrity by providing an alternative power path without occupying core circuit layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If input/output pads are arranged along edges of the chip for ease of wire-bonding, then wire-bonding process is simplified, but power path becomes longer and parasitic resistance increases
Solution Approach 1:
The chip pad structure is segmented into two distinct types: common pads arranged at peripheral edges for wire-bonding connections, and core pads located in the central region for power distribution to devices. This segmentation allows I/O pads to be positioned at edges for manufacturing ease while core pads provide short power paths from the chip center, resolving the contradiction between ease of wire-bonding and power integrity.
Solution Approach 2:
The patent introduces an intermediary power distribution network consisting of core pads and associated wiring that acts as a mediator between the peripheral common pads and the central devices. This intermediary structure provides dedicated power paths that bypass the long peripheral routes, thereby maintaining power integrity without compromising the wire-bonding process simplicity.
2Quantity of substance
If chip size is increased to accommodate more devices, then device capacity is improved, but IR drop effect becomes more severe
Solution Approach 1:
The patent transitions from a one-dimensional peripheral power distribution approach to a two-dimensional power distribution architecture. Core pads are distributed across the central chip area in a planar arrangement, creating multiple short power paths radiating from the chip center. This dimensional change allows larger chip sizes to accommodate more devices while maintaining short power paths, thereby preventing IR drop from becoming severe as chip size increases.
3Reliability
If power path is shortened to reduce parasitic resistance, then power integrity is improved, but layout flexibility is reduced
Solution Approach 1:
The patent applies local quality by positioning core pads specifically in the central region of the chip where devices are located, rather than uniformly distributing all pads across the entire chip. This localized pad arrangement provides short power paths precisely where needed (in the chip center) while leaving peripheral regions free for other functions, thereby maintaining layout flexibility despite the shortened power paths.
Data Source
AI summary
An electronic package structure and a chip thereof are provided. The electronic package structure includes a supporting element, a chip, an internal bonding wire, and a plurality of external bonding wires. The supporting element has a chip arrangement portion. The chip has a first surface and a second surface opposite to the first surface. The chip is arranged on the chip arrangement portion with the second surface facing toward the supporting element. The chip includes a first common pad and an individual core pad that are disposed on the first surface. The internal bonding wire is connected between the first common pad and the individual core pad. The external bonding wires are connected between the chip and the supporting element, in which a first external bonding wire of the external bonding wires and the internal bonding wire are jointly connected to the first common pad.