Chip Package Structure with Pre-patterned Structures for Electrical Connectivity
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Solution Overview
Problem
Conventional through molding compound technology for increasing electrical connectivity in chip package structures is costly and inefficient.
Innovation Solution
A chip package structure and manufacturing method that includes a chip module, pre-patterned structures, a filling material layer, and a redistribution layer, where the pre-patterned structures are placed around the chip, and the filling material layer encapsulates the chip and structures with surfaces that are substantially co-planar, allowing for efficient electrical connection and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through molding compound technology is applied to increase electrical connectivity density, then the electrical connection density is improved, but the manufacturing cost increases
Solution Approach 1:
The patent divides the package structure into separate functional components: pre-patterned structures containing circuits are separated from the chip module, and electrical connections are established through controlled vias in the filling material layer rather than through complete penetration of structural layers. This segmentation allows for more cost-effective manufacturing while achieving the required electrical connectivity density.
Solution Approach 2:
The patent transitions from conventional through-layer connections (vertical dimension only) to a multi-dimensional connection approach where pre-patterned structures are positioned around the chip module in a planar arrangement, and electrical connections are made through the filling material layer at a different vertical level, creating connections in multiple spatial dimensions.
2Quantity of substance
If conventional through molding compound technology is used, then electrical connectivity is achieved, but the coating process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-patterning the circuit structures and positioning them around the chip module before the encapsulation process. The filling material layer is then applied to encapsulate both the chip and pre-patterned structures simultaneously, creating a simplified coating process compared to conventional methods that require multiple sequential coating and drilling operations.
Solution Approach 2:
The patent merges the encapsulation function and the electrical connection function into a single filling material layer. This layer simultaneously provides mechanical protection for the chip and pre-patterned structures while serving as the medium for electrical connections through embedded vias, thereby reducing overall process complexity.
3Reliability
If traditional manufacturing methods are used, then package structure is formed, but manufacturing cost and process time increase
Solution Approach 1:
The patent performs preliminary positioning of pre-patterned structures around the chip module before encapsulation, allowing for parallel processing and reduced manufacturing steps. The filling material layer is then applied in a single encapsulation operation that simultaneously protects all components and establishes electrical connection pathways, significantly improving manufacturing efficiency while maintaining structural integrity.
Data Source
AI summary
A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit.