Chip Package Recess Design for Miniaturization
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Solution Overview
Problem
The existing chip packaging processes result in increased package size due to external conducting structures, making it difficult to further miniaturize chip packages while also posing challenges in preventing short circuits and ensuring reliability.
Innovation Solution
A chip package design featuring a semiconductor substrate with recesses and spacers, where conducting layers extend into the recesses, reducing the height of conducting structures and preventing short circuits by positioning spacers between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external conducting structures (wires or solder balls) are formed on the substrate, then electrical connection paths are provided, but the entire size of the chip package increases
Solution Approach 1:
The conducting layer transitions from a traditional planar configuration to a three-dimensional structure by extending into the recess. This vertical integration into the substrate depth allows electrical connections to be established without increasing the lateral footprint of the chip package, effectively utilizing the Z-dimension to reduce overall package volume while maintaining connection functionality.
Solution Approach 2:
The conducting layer is nested within the recess structure, with the spacer positioned between the conducting layer and the side edge of the substrate. This nested arrangement integrates multiple functional elements (conducting path, isolation structure) within the same spatial envelope, eliminating the need for separate external conducting structures and reducing the chip package size.
2Volume of moving object
If conducting layers extend into the recess, then the height of conducting structures is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The recess is formed in the substrate before the conducting layer is deposited. This preliminary structuring of the substrate provides a pre-defined template that guides the subsequent conducting layer formation, ensuring proper positioning and depth control. The spacer is also positioned in advance during recess formation, establishing precise geometric constraints that facilitate accurate conducting layer deposition without requiring ultra-precise simultaneous multi-step alignment.
Data Source
AI summary
A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.