Chip Package Recess Section Mitigates Thermal Stress Delamination
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Solution Overview
Problem
Conventional chip packages experience delamination due to differing thermal expansion coefficients of semiconductor wafers, spacers, and glass substrates, leading to electrical failures from water vapor and air permeation when exposed to high temperatures.
Innovation Solution
A chip package design featuring a recess section between the semiconductor substrate, spacer, and packaging layer, creating a non-continuous side surface to mitigate thermal stress and prevent delamination, along with a fabrication method that forms separate spacers between chips to enhance bonding and reduce permeation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous side surface structure is used in conventional chip packages, then the packaging is simple to manufacture, but thermal stress causes delamination between layers when exposed to high temperature
Solution Approach 1:
The side surface is segmented into multiple sections with different heights, creating a stepped configuration. The first side surface section has a first height and the second side surface section has a second height different from the first height, dividing the continuous surface into discrete segments that can accommodate differential thermal expansion independently.
Solution Approach 2:
The side surface employs an asymmetric stepped design where different sections have different heights rather than a uniform continuous surface. This asymmetric structure allows each section to respond differently to thermal stress, preventing the uniform expansion that causes delamination in conventional continuous side surface designs.
2Adaptability or versatility
If materials with different thermal expansion coefficients are used for semiconductor wafer, spacer, and glass substrate, then the packaging can accommodate different material requirements, but thermal expansion differences cause delamination at high temperature
Solution Approach 1:
The side surface is divided into multiple sections with different heights, allowing each section to accommodate the thermal expansion characteristics of different materials independently. This segmentation prevents the propagation of thermal stress across the entire structure, maintaining bonding stability despite material differences.
Solution Approach 2:
Different sections of the side surface are given different heights to create localized structural properties. The first and second side surface sections have distinct heights tailored to accommodate the specific thermal expansion requirements of the materials in those regions, optimizing local bonding stability.
3Reliability
If delamination occurs between semiconductor wafer, spacer, and glass substrate, then the structure can accommodate thermal expansion, but water vapor and air permeate into the package causing electrical failure
Solution Approach 1:
The stepped side surface structure segments the packaging layers, creating a configuration that accommodates thermal stress without causing delamination. By dividing the continuous side surface into sections with different heights, the structure manages thermal expansion differences while maintaining the integrity of the sealing barrier against water vapor and air permeation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The non-continuous side surface design reduces thermal stress and prevents delamination, thereby enhancing the reliability and reducing electrical failures in chip packages by minimizing water vapor and air permeation.
Implementation Method 1
Because the materials of the semiconductor wafer, the spacer and the glass substrate are different, thermal expansion coefficients thereof are also different. When the conventional chip packages are exposed to a high temperature, delamination occurs between the semiconductor wafer, the spacer and the glass substrate.
Data Source
AI summary
A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.