Chip Package Recesses for Wire Density and Solder Protection
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Solution Overview
Problem
The challenge in chip packaging is to densely integrate conducting wires within a limited space to reduce the size of electronic products while ensuring protection and efficient signal transmission, which existing technologies have not adequately addressed.
Innovation Solution
A chip package design featuring a semiconductor substrate with recesses that house a wire layer and insulating layers, allowing for a more compact layout of conducting structures and improved signal transmission, along with a solder wire within the recesses for enhanced reliability and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more conducting wires are disposed in a limited space, then the density of conducting wires is improved, but the complexity of packaging process increases
Solution Approach 1:
The patent transitions from planar wire arrangement to three-dimensional routing by extending wires into recesses formed in the semiconductor substrate. This vertical dimension allows additional conducting wires to be accommodated within the same footprint area, increasing wire density without proportionally increasing process complexity
Solution Approach 2:
The wire layer is nested within the recesses of the semiconductor substrate, with the insulating layer nested between the wire layer and substrate. This nested structure allows multiple conducting wires to be packed into the limited space by utilizing the vertical depth of the recesses rather than only horizontal expansion
2Volume of moving object
If the size of chip package is reduced, then the size of electronic products is improved, but the reliability of solder wire connection deteriorates
Solution Approach 1:
The solder wire is nested within the recesses of the semiconductor substrate, which provides physical protection and constraint. This nesting structure maintains connection reliability by preventing solder wire damage while reducing the overall chip package size, as the recesses provide a protective cavity for the solder wire
Solution Approach 2:
The insulating layer acts as a protective shell between the wire layer and semiconductor substrate, providing isolation and protection while maintaining a compact structure. This thin film approach allows for size reduction while preserving functional reliability
Data Source
AI summary
An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.