Chip Package Recessed Structure for Size Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip packaging processes are costly and time-consuming due to multiple patterning and material-deposition processes, necessitating a simplified and fast technique for forming chip packages.
Innovation Solution
A chip package design featuring a first recess extending from the upper surface toward the lower surface along the sidewall, with a second recess extending from the first recess's bottom toward the lower surface, and a redistribution layer electrically connected to the signal pad region, allowing for reduced size and increased sensitivity through recessed structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multiple patterning and material-deposition processes are used, then manufacturing precision is maintained, but manufacturing cost increases and processing time extends
Solution Approach 1:
The chip package structure is segmented into distinct functional zones: a first recess extending from the upper surface toward the lower surface along the sidewall, and a second recess extending from the first bottom toward the lower surface. This segmentation allows different regions to serve different purposes (signal routing, structural support, encapsulation) without requiring complex multi-step patterning processes, thereby maintaining precision while reducing processing time
Solution Approach 2:
The invention transitions from conventional planar chip package design to a three-dimensional structure with recesses extending in vertical and lateral dimensions. The first and second recesses create depth variations that enable signal routing and structural functions within the vertical dimension, reducing the need for additional lateral patterning steps and material depositions
2Volume of moving object
If chip package size is reduced through recessed structures, then sensitivity is enhanced, but structural strength may be compromised
Solution Approach 1:
The recessed structure is divided into two segments: the first recess extending from the upper surface and the second recess extending from the first bottom. This segmentation allows the upper portion to be optimized for size reduction and sensitivity enhancement, while the lower portion maintains structural integrity by providing anchoring points for the redistribution layer and ensuring adequate mechanical strength
Solution Approach 2:
The first recess extends further laterally than the second recess, creating an asymmetric structure. This asymmetry allows the upper portion to be more compact for enhanced sensitivity, while the lower portion maintains sufficient width for structural strength. The redistribution layer is positioned to exploit this asymmetric geometry for optimal electrical connection
3Measurement precision
If encapsulant layer thickness is minimized to enhance sensitivity, then chip package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The first and second recesses are formed preliminarily before the encapsulant layer is applied. This preliminary structuring defines the exact regions where encapsulation is needed, allowing the encapsulant to be deposited only in necessary areas with controlled thickness. The recess geometry itself serves as a template that simplifies subsequent encapsulation processing rather than requiring additional patterning steps
Data Source
AI summary
A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.