Chip Package Redistributing Metal Layer Side Bonding
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Solution Overview
Problem
Existing chip packages require large wire-bonding areas, limiting the space for interconnections and hindering the miniaturization of semiconductor chips while increasing their functions.
Innovation Solution
A chip package design featuring a semiconductor chip with an isolation layer and a redistributing metal layer that reduces the wire-bonding area by positioning bonding pads on one side, allowing for denser bonding and more efficient interconnections without the need for a bonding-wire carrier to enter holes, thereby increasing the volume available for interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If large wire-bonding area is provided to accommodate bonding-wire carrier entry, then bonding process is enabled, but space for interconnections in the semiconductor chip is limited
Solution Approach 1:
The patent moves the bonding pads from the traditional upper surface to the lower surface of the semiconductor chip, utilizing the third dimension (depth/thickness) to resolve the space conflict. This allows bonding wire connections to be established from below, eliminating the need for large hole structures and bonding-wire carrier entry space on the upper surface, thereby freeing up interconnection space while maintaining bonding capability
Solution Approach 2:
Instead of bonding from the upper surface as in conventional designs, the patent inverts the bonding approach by positioning bonding pads on the lower surface and establishing connections from below. This inversion eliminates the need for deep holes and large bonding areas on the upper surface, resolving the contradiction between bonding requirements and interconnection space
2Ease of manufacture
If deep holes are etched to expose I/O conducting pads, then wire bonding is enabled, but chip area for interconnections is reduced
Solution Approach 1:
The patent extracts the bonding pad structure from the traditional upper surface location and relocates it to the lower surface. This extraction eliminates the need for deep etching holes to expose I/O pads, as the bonding pads are now directly accessible from below without requiring volumetric hole structures, thereby preserving chip area for interconnections
Solution Approach 2:
By relocating bonding pads to the lower surface, the patent utilizes the vertical dimension to access I/O connections without creating deep horizontal holes. This dimensional change eliminates the trade-off between hole depth and available chip area, allowing full utilization of chip area for interconnections while maintaining wire bonding capability
Data Source
AI summary
A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.