Chip Package With Redistribution Layers And Bonding Balls
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Solution Overview
Problem
The increasing demand for miniaturized and complex electronic and optoelectronic products poses a challenge in maintaining or reducing the size of semiconductor chip packages while ensuring operational stability and electrical connectivity.
Innovation Solution
A chip package design featuring a substrate with conductive pads, redistribution layers (RDLs), and encapsulation layers, along with conductive structures and bonding balls, allows for efficient electrical connections between chips and external circuits, enabling the integration of multiple functionalities within a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of chip packages is increased to meet the demand for complex functionality, then the functionality and performance of electronic products are improved, but the size of electronic products increases
Solution Approach 1:
The patent combines multiple chip packages into a single integrated package structure. Multiple chips are mounted on a common substrate and encapsulated together, allowing multiple functionalities to be integrated in one package rather than requiring separate packages for each function.
Solution Approach 2:
The patent transitions from a two-dimensional arrangement of separate chip packages to a three-dimensional integrated structure. By stacking chips and using vertical interconnections through the substrate, the design utilizes the vertical dimension to increase functionality without proportionally increasing the horizontal footprint.
2Volume of moving object
If the size of chip packages is reduced to maintain compact product dimensions, then the portability of electronic products is improved, but the electrical connectivity and operational stability may be compromised
Solution Approach 1:
The patent uses an encapsulation layer that conforms to the three-dimensional arrangement of chips and interconnections. This flexible encapsulation approach provides protective coverage while accommodating the compact vertical structure, ensuring environmental protection without requiring excessive package size.
Solution Approach 2:
The substrate serves as an intermediary platform that provides mechanical support and electrical interconnection between multiple chips. It enables compact integration while maintaining reliable electrical pathways, acting as a mediator that allows size reduction without compromising connectivity.
3Volume of moving object
If multiple chips are integrated into a single package to reduce the number of packages, then the size is reduced, but the complexity of the package structure increases
Solution Approach 1:
The patent divides the integrated package into distinct functional layers and modules: substrate, multiple chips, encapsulation layer, and interconnection structures. This segmentation allows each component to be optimized and manufactured separately before integration, managing complexity through modular design.
Solution Approach 2:
The substrate performs multiple functions simultaneously: providing mechanical support for chips, serving as an electrical interconnection platform, and acting as a mounting base for the encapsulation layer. This multi-functionality reduces the need for additional separate components, simplifying the overall package structure despite integrating multiple chips.
Data Source
AI summary
A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.