Chip Package With Redistribution Layers And Buffer
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Solution Overview
Problem
Conventional wafer-level packages face issues such as poor electrical contact, warping of wafers, shorts between conducting wires, and planarization difficulties, which hinder effective packaging of semiconductor chips.
Innovation Solution
A chip package design featuring a semiconductor substrate with a conducting pad, an insulating layer, and redistribution layers that ensure electrical contact and prevent shorts, along with a buffer layer to prevent direct contact between redistribution layers and the substrate, and a light-sensitive insulating layer for planarization, facilitating efficient packaging and dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer-level packaging is used, then the packaging process is simple, but electrical contact is poor and shorts between conducting wires occur
Solution Approach 1:
The packaging structure is segmented into multiple functional layers: insulating layer, first redistribution layer, second redistribution layer, and buffer layer. Each layer performs a specific function to ensure reliable electrical contact while preventing shorts, thereby resolving the contradiction between reliability and complexity by organizing complexity into manageable segments.
Solution Approach 2:
The patent transitions from conventional planar packaging to a multi-layer vertical structure. Conducting wires are arranged in different layers (first redistribution layer and second redistribution layer) separated by insulating layers, utilizing the vertical dimension to prevent shorts while maintaining electrical connectivity, thus improving reliability without excessive complexity.
2Productivity
If wafer-level packaging is used, then packaging efficiency is high, but warping of wafers occurs
Solution Approach 1:
The buffer layer is strategically positioned between the second redistribution layer and the semiconductor substrate, providing localized mechanical support and stress relief at critical areas. This local reinforcement prevents warping while maintaining the overall efficiency of the wafer-level packaging process.
3Manufacturing precision
If conventional packaging structure is used, then manufacturing is simple, but planarization is difficult
Solution Approach 1:
The insulating layer is formed with a thickness greater than the height of conducting wires before subsequent processing steps. This preliminary action creates a planar surface that facilitates easier and more precise planarization in later manufacturing steps, improving manufacturing precision while the modular structure keeps overall complexity manageable.
Data Source
AI summary
A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.