Chip Package Redistribution Layer Using a Malleable Carrier
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Solution Overview
Problem
Current semiconductor chip packaging is costly and time-consuming due to serial processes like wire bonding, which are unsuitable for large substrates and require dedicated equipment, and struggle with integrating power and logic chips effectively, especially with the need for fine structures and thick metal lines.
Innovation Solution
A method using a malleable carrier with an electrically conductive layer to form a redistribution layer around the chip, enabling batch processing and hetero-integration of logic and power chips through deep drawing and ultrasonic welding, soldering, or conductive glue, allowing for flexible and precise 3D interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding process is used for chip packaging, then electrical connection is achieved, but processing time increases and cost increases
Solution Approach 1:
The patent merges the electrical connection function with the mechanical support function by integrating the conductive layer directly into the packaging structure. The conductive layer serves both as the electrical interconnect replacement and as part of the package substrate, eliminating the need for separate wire bonding process
Solution Approach 2:
The patent extracts the wire bonding process from the packaging flow by replacing it with a conductive layer that is already integrated into the package structure. The electrical connections are established through the conductive layer during the molding process itself, removing the time-consuming wire bonding step
2Reliability
If leadframe and wire bonding process is used, then chip packaging is achieved, but material cost increases
Solution Approach 1:
The conductive layer serves multiple functions simultaneously: it provides electrical interconnect, acts as part of the package substrate, and enables hetero-integration of different chip types. This multi-functionality eliminates the need for separate leadframe and wire bonding materials
Solution Approach 2:
The patent discards the traditional leadframe structure in favor of a molded package with integrated conductive layer. The conductive layer is formed directly within the mold cavity, eliminating material waste associated with leadframe fabrication and wire bonding
3Adaptability or versatility
If dedicated equipment for each package platform is used, then specific packaging requirements are met, but device complexity increases
Solution Approach 1:
The molding process with integrated conductive layer formation serves as a universal platform for packaging different chip types including logic chips and power chips. The same mold can be configured for different package types, eliminating the need for dedicated equipment for each package platform
Solution Approach 2:
The patent merges multiple packaging functions into a single molding process that simultaneously achieves chip enclosure, electrical interconnect formation, and structural support. This consolidation reduces equipment complexity compared to separate processes for each function
4Reliability
If thermosonic wire bonding is used on big areas, then electrical connection is achieved, but oxidation problems occur
Solution Approach 1:
The patent extracts the high-temperature wire bonding process that causes oxidation and replaces it with a conductive layer formation process that occurs at lower temperatures during molding, eliminating the oxidation problem while maintaining electrical connection reliability
Solution Approach 2:
The conductive layer acts as an intermediary that provides electrical connection without requiring direct high-temperature contact between bonding surfaces. The layer is formed through molding at controlled temperatures that prevent oxidation, serving as a protective mediator
5Adaptability or versatility
If fine structures and thick lines are required for hetero-integration, then logic and power chips can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The conductive layer is formed with locally optimized properties: fine trace structures for logic chip connections and thick copper regions for power chip connections. The layer thickness and conductivity are varied locally to meet different electrical requirements of different chip types
Solution Approach 2:
The patent changes the physical parameters of the conductive layer including thickness, conductivity, and trace width in different regions to accommodate both fine structures for logic and thick lines for power. The molding process allows continuous parameter variation within the same structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces costs and processing time by using parallel processes, improves precision, and enables robust mechanical stability while accommodating different chip technologies, facilitating the integration of logic and power chips with varying metal thickness requirements.
Implementation Method 1
deep drawing and ultrasonic welding, soldering, or conductive glue, allowing for flexible and precise 3D interconnects
Implementation Method 2
deep drawing and ultrasonic welding, soldering, or conductive glue
Data Source
AI summary
A method of forming a chip package is provided. The method includes providing a malleable carrier with a layer of an electrically conductive material formed thereon, and positive fitting the malleable carrier to a chip to at least partially enclose the chip with the malleable carrier. The layer at least partially physically contacts the chip, such that the layer electrically contacts a chip contact of the chip. The layer forms a redistribution layer.