Semiconductor Chip Package with Vertical Redistribution Layers
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Solution Overview
Problem
The semiconductor chip packaging industry faces challenges in producing compact, multi-functional chips with high yield and low production costs, as the manufacturing process becomes more complex due to downsizing and increased complexity, leading to higher costs and lower production rates.
Innovation Solution
A chip package design featuring dual redistribution layers that electrically connect the conductive pad on the upper surface to solder balls or wires on the lower surface, allowing for a thicker semiconductor chip without the need for thinning or a carrier substrate, reducing production costs and improving mechanical strength and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor chip is made thinner to reduce package size, then the compact form factor is achieved, but the mechanical strength decreases and production yield becomes more difficult to maintain
Solution Approach 1:
The patent introduces vertical redistribution layers that extend through the chip thickness, creating electrical connections in the vertical dimension rather than requiring thin lateral connections. This allows the chip to maintain greater thickness for mechanical strength while achieving compact packaging through vertical integration of connection paths.
2Adaptability or versatility
If the semiconductor chip is made thinner to enable stacking, then the stacking capability is improved, but the need for carrier substrate increases production cost
Solution Approach 1:
The patent segments the electrical connection function into separate redistribution layers formed directly on the chip, eliminating the need for a carrier substrate. The chip is divided into functional regions with redistribution layers at different depths, allowing stacking without requiring additional substrate materials.
Solution Approach 2:
The patent creates vertical electrical pathways through the chip using redistribution layers that extend through the chip thickness, enabling stacking in the vertical dimension without requiring thinning or carrier substrates. This vertical connection approach allows direct chip-to-chip stacking.
3Reliability
If dual redistribution layers are added to achieve electrical connection, then the electrical connectivity is improved, but the device complexity increases
Solution Approach 1:
The patent merges the electrical connection function into the chip structure itself by forming redistribution layers directly on the chip substrate. The first and second redistribution layers are integrated with the chip's internal wiring, combining multiple functions (structural support, electrical connection, and signal distribution) into a unified structure rather than adding separate components.
Data Source
AI summary
A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.