Chip Package Redistribution Layer via Segmented Solder Mask
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Solution Overview
Problem
Conventional chip package structures face challenges with fine-pitch pad arrangements, leading to increased aspect ratios of solder mask openings, making precise alignment and reflow processes difficult, which can result in bridge effects and short-circuits.
Innovation Solution
A method involving a carrier with a metal layer and patterned photoresist layer to form connection terminals and redistribution layers, allowing for precise alignment and rearrangement of electrical contact points, thereby preventing short-circuits and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimension of the openings of the solder mask layer is reduced to comply with fine pitch among pads, then the pitch among pads is reduced, but the aspect ratio of the openings increases making alignment and reflow difficult
Solution Approach 1:
The invention divides the solder mask layer into multiple separate layers, each with its own openings. This segmentation allows each layer to have larger, easier-to-align openings while collectively achieving fine pitch among pads through the stacked configuration of multiple layers.
Solution Approach 2:
The invention transitions from a single-plane solder mask structure to a multi-layer stacked structure, adding the vertical dimension. This allows the horizontal pitch to be reduced while each individual layer maintains larger opening dimensions for better alignment precision.
2Quantity of substance
If the dimension of the openings of the solder mask layer is reduced to comply with fine pitch among pads, then the pitch among pads is reduced, but bridge effects and short-circuit conditions occur during reflow
Solution Approach 1:
By segmenting the solder mask into multiple layers with separate openings, each opening can be larger and better defined, preventing solder bridge formation during reflow while maintaining fine pitch among pads through the multi-layer configuration.
Solution Approach 2:
The multiple solder mask layers act as intermediaries between adjacent pads, providing physical separation and control over solder flow paths. This prevents direct contact between solder on adjacent pads, eliminating short-circuit risks while enabling fine pitch design.
3Quantity of substance
If the aspect ratio of the openings is increased to achieve fine pitch, then the pitch among pads is reduced, but the printing or placement of large solder bumps becomes difficult
Solution Approach 1:
The solder mask structure is segmented into multiple layers, allowing each layer to have larger opening dimensions that facilitate easier printing and placement of solder bumps, while the stacked configuration collectively achieves fine pitch among pads.
Solution Approach 2:
By adding the vertical dimension with multiple solder mask layers, each layer can have larger opening sizes for easier manufacturing, while the combined structure achieves the required fine horizontal pitch among pads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures precise alignment of solder materials and prevents short-circuits during reflow, improving manufacturing efficiency and reducing costs by simplifying the process and enhancing yield.
Implementation Method 1
A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer.
Implementation Method 2
A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer.
Implementation Method 3
Through reflow, the substrate and the chip are electrically and structurally connected by means of the solder bumps located between the substrate and the chip.
Data Source
AI summary
A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.