Electronic Chip Package With Double-Sided Redistribution Structure
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Solution Overview
Problem
Conventional electronic chip packages face limitations in thermal insulation and complexity, especially when dealing with high-power applications and complex electronic circuits, which affect the performance and reliability of the chips.
Innovation Solution
The proposed solution involves an electronic component architecture with an electrically conductive mounting structure and a redistribution structure on both sides of the chip, embedded in an insulating matrix, allowing for double-sided electrical connection and flexible wiring configurations, along with a periphery connection structure for easy integration with electronic peripheries, enabling efficient heat dissipation and high-power applications without requiring adaptations to existing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional packaging structures are used for electronic chips, then the package can be manufactured with standard processes, but the thermal insulation within the package degrades heat dissipation performance
Solution Approach 1:
The patent introduces a third dimension by stacking multiple electronic chips vertically between a mounting structure and a redistribution structure, creating a three-dimensional integrated package. This vertical stacking enables improved heat dissipation through the z-direction while maintaining compact footprint, resolving the contradiction between heat dissipation performance and package structure complexity.
Solution Approach 2:
The patent employs composite material structures including dielectric layers with embedded conductive vias, combining electrically insulating materials with thermally conductive pathways. This composite approach allows simultaneous electrical isolation and thermal management, improving heat dissipation without compromising package integrity or requiring excessive structural complexity.
2Adaptability or versatility
If bond wires are used to connect electronic chips to leadframes, then the connection process is simple, but the architecture reaches limits when complex electronic circuits are required
Solution Approach 1:
The patent segments the connection architecture into distinct functional layers: mounting structure for mechanical support, conductive layers for electrical connection, dielectric layers for isolation, and redistribution structure for circuit routing. This segmentation enables complex electronic circuits to be implemented through systematic layer stacking and via connections, providing adaptability without overwhelming structural complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar connections to three-dimensional vertical interconnections through stacked conductive layers and vias. This dimensional change enables complex circuit architectures by routing signals through multiple layers and directions, significantly enhancing adaptability for complex electronic circuits while maintaining manageable structural complexity through standardized layering.
3Power
If electronic chips are mounted on leadframes with bond wire connections, then the manufacturing process is conventional, but thermal management and high-power applications are limited
Solution Approach 1:
The patent implements vertical stacking of multiple conductive layers and chips in the z-direction, creating three-dimensional current paths and thermal conduction pathways. This dimensional change enables high-power applications by providing multiple parallel conduction paths and improved heat sinking through the stack, significantly enhancing power capability while maintaining ease of manufacture through standardized sequential fabrication processes.
Solution Approach 2:
The patent uses composite structures combining conductive materials for electrical pathways, dielectric materials for insulation, and thermally conductive materials for heat management. This composite material approach enables high-power applications by simultaneously providing electrical connection, electrical isolation, and thermal management functions, enhancing power capability without complicating the manufacturing process.
4Adaptability or versatility
If standard packaging concepts are used, then compatibility with existing systems is maintained, but flexibility in wiring configurations and heat removal paths is restricted
Solution Approach 1:
The patent segments the package architecture into modular functional units (mounting structure, conductive layers, dielectric layers, redistribution structure) that can be independently designed and configured. This segmentation provides wiring configuration flexibility by allowing custom routing patterns in each layer while maintaining overall package compatibility, achieving adaptability without excessive structural complexity.
Solution Approach 2:
The patent adds vertical dimensionality with stacked layers and vias, enabling three-dimensional wiring configurations that provide flexible signal routing and heat removal paths. This dimensional enhancement allows complex wiring patterns to be implemented through layer stacking rather than planar complexity, improving adaptability while keeping the package architecture manageable through systematic vertical integration.
Data Source
AI summary
An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.