Chip Package Redistribution Layer via Through-Silicon Vias
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Solution Overview
Problem
The existing chip packaging process is costly and inefficient due to the use of gold wires and lead frames for external electrical connections, which also limits the miniaturization of chip packages.
Innovation Solution
A chip package design featuring a redistribution layer that penetrates through substrates to electrically connect conductive pads, eliminating the need for gold wires and lead frames by using a wafer-level packaging process with through-silicon vias, allowing for vertical stacking and reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wires and lead frames are used for external electrical connections, then reliable electrical connection is achieved, but manufacturing cost increases and package size increases
Solution Approach 1:
The patent extracts and eliminates the lead frame and gold wire components from the packaging structure. Instead of using these separate external connection elements, the invention integrates electrical connections directly into the substrate through through-silicon vias that extend from the front surface to the back surface, removing the need for costly gold wires and lead frames while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent merges the electrical connection function into the substrate itself by creating through-silicon vias that provide direct electrical pathways. This combines what were previously separate components (substrate, lead frame, and gold wires) into an integrated structure where the substrate performs both mechanical support and electrical connection functions, reducing overall package size and cost.
2Reliability
If gold wires and lead frames are used for external electrical connections, then reliable electrical connection is achieved, but package size increases
Solution Approach 1:
The patent extracts and eliminates the lead frame and gold wire components from the packaging structure. Instead of using these separate external connection elements, the invention integrates electrical connections directly into the substrate through through-silicon vias that extend from the front surface to the back surface, removing the need for costly gold wires and lead frames while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent transitions from a planar two-dimensional connection approach (using lead frames and wires on the package perimeter) to a three-dimensional vertical connection approach (using through-silicon vias that penetrate the substrate thickness). This dimensional change allows electrical connections to be made through the substrate rather than around its edges, significantly reducing the package's horizontal footprint and enabling miniaturization.
3Ease of manufacture
If wafer-level packaging process with through-silicon vias is used, then manufacturing cost decreases and package size decreases, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the through-silicon vias and conducting pads on the substrate before the dicing step that separates individual chips. This preliminary structuring allows subsequent packaging operations to proceed more efficiently and at lower cost, as the electrical connection infrastructure is already in place. The wafer-level processing enables batch manufacturing of multiple chips with integrated connection structures.
Solution Approach 2:
The patent replaces the mechanical wire-bonding system with a direct conductive via system. Instead of mechanically attaching gold wires to lead frames and substrates, the invention uses vertically extending conductive pathways formed through the substrate material itself, eliminating the need for complex wire bonding equipment and processes while reducing manufacturing steps.
Data Source
AI summary
A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.