Chip Package Ring Structure for Thermal Warpage Control
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Solution Overview
Problem
The challenge of forming a reliable chip package structure is exacerbated by the mismatch in thermal expansion coefficients between chips and wiring substrates, leading to package warpage and stress, which affects structural integrity and reliability, especially in advanced packaging technologies like CoWoS and InFO.
Innovation Solution
A hybrid ring and lid structure is introduced, comprising a first ring with low thermal expansion coefficient and high rigidity, combined with a substrate to form a low CTE equivalent body, and a second ring with higher thermal expansion coefficient to manage warpage and stress through controlled stepwise warpage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a chip package structure is formed with chips and wiring substrate having different coefficients of thermal expansion, then the package can be manufactured, but package warpage and stress occur affecting structural integrity
Solution Approach 1:
The patent introduces a ring structure with specifically engineered coefficient of thermal expansion (CTE) values that differ from both the chip and wiring substrate. By changing the CTE parameter of the ring structure, it creates a gradient that compensates for thermal mismatch, reducing warpage and stress while maintaining manufacturability
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties (chip, ring structure, wiring substrate). This composite approach allows each layer to contribute its specific properties, with the ring structure acting as a buffer that reconciles the thermal expansion differences between the chip and substrate
2Device complexity
If traditional packaging structures are used, then manufacturing is simple, but warpage and stress affect reliability in advanced packaging technologies
Solution Approach 1:
The patent divides the packaging structure into distinct segments: the chip, the ring structure, and the wiring substrate. This segmentation allows independent optimization of each component's properties, particularly the ring structure's CTE, to manage thermal stress without requiring complete redesign of the entire package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid structure effectively reduces package warpage and stress, enhancing structural integrity, coplanarity, and yield in semiconductor devices by managing thermal cycling and reliability tests.
Implementation Method 1
a first ring structure over the wiring substrate and surrounding the chip structure. A first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate
Implementation Method 2
an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.