Wafer-Level Chip Package With Segmented Spacers
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Solution Overview
Problem
Wafer level chip packaging faces challenges in maintaining the precision and sensitivity of electronic components during manufacturing, as contamination and high manufacturing costs are significant issues, especially in mass production where maintaining sterile conditions is costly and prone to lower yields and product contamination.
Innovation Solution
The method involves forming outer and inner spacers around semiconductor chips to isolate electronic components, using a protection lid to create a compartment, and employing thermal or UV curing materials to support mechanical pressure during dicing, ensuring the components are protected from contamination and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sterile conditions are maintained during manufacturing, then product contamination is reduced, but manufacturing cost increases
Solution Approach 1:
The patent divides the protection structure into multiple segments: outer spacers formed between adjacent chips, inner spacers formed around each electronic component, and a protection lid. This segmented approach creates isolated compartments for each component while maintaining cost-effective manufacturing through wafer-level processing
Solution Approach 2:
The spacers and protection lid are formed before the dicing process, creating a preliminary protective structure that prevents contamination during subsequent manufacturing steps. The outer spacers are formed first, followed by inner spacers, and finally the protection lid is deposited to seal the components
2Reliability
If protection structures are added to isolate components, then component protection is improved, but device complexity increases
Solution Approach 1:
The spacers serve multiple functions: they physically isolate electronic components from each other, provide structural support during dicing, and define compartments for the protection lid. The protection lid simultaneously protects multiple components across the wafer while being formed as a single continuous layer
Solution Approach 2:
The patent implements a nested protection structure where inner spacers are formed within compartments defined by outer spacers, and the protection lid encloses both spacer systems. This nested arrangement provides multi-level protection while efficiently using vertical space
3Reliability
If spacers are used to support mechanical pressure during dicing, then component damage is reduced, but manufacturing process complexity increases
Solution Approach 1:
The spacers are formed beforehand to provide mechanical support and cushioning during the dicing process. The outer spacers absorb mechanical stress from the dicing blade, while inner spacers protect individual components, preventing damage before it can occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances the protection of electronic components from contamination and mechanical damage, and simplifies the dicing process by maintaining the integrity of the components and preventing residue attachment, thus improving the reliability of chip package production.
Implementation Method 1
a protection lid is disposed on top of the outer and inner spacers such that the electronic component on the semiconductor chip is isolated in an compartment defined by the protection lid, inner and outer spacers
Implementation Method 2
the outer and inner spacers can sustain certain mechanical pressure in the step of dicing semiconductor chips. In the presence of the spacers, the protection lid will not distort wildly because of strong external force
Data Source
AI summary
A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.