Chip Package Integrating Sensing and IC on Single Substrate
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Solution Overview
Problem
The existing chip packaging process limits the miniaturization of electronic products due to the separate and independent disposition of sensing and integrated circuit chips on printed circuit boards, making it difficult to reduce the size of electronic devices.
Innovation Solution
A chip package design that integrates a sensing device and an integrated circuit device on a single substrate using a redistribution layer for electrical connection, with an insulating layer and conducting structures to facilitate compact packaging, allowing for the integration of multiple functions in a smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If sensing device and integrated circuit device are separately disposed on printed circuit board, then electrical connection can be established, but the size of printed circuit board cannot be reduced
Solution Approach 1:
The patent merges the sensing device and integrated circuit device onto a single substrate, eliminating the need for separate discrete components and their interconnections. This consolidation directly reduces the overall size of the printed circuit board while maintaining all necessary electrical connection functions through integrated routing layers.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout of separate components to a three-dimensional stacked architecture where the sensing device and integrated circuit device are vertically arranged on different layers of the substrate. This dimensional change enables compact integration while preserving electrical connectivity through vertical vias and redistribution layers.
2Volume of moving object
If multiple chips are integrated on single substrate, then miniaturization is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary integration of the sensing device and integrated circuit device onto the substrate during the wafer fabrication process itself, before final packaging. This preliminary action on the wafer level enables subsequent batch processing and assembly operations to be performed more efficiently, reducing overall manufacturing complexity despite the integrated architecture.
Data Source
AI summary
A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.


