Chip Package Sensing Region Recess for Enhanced Sensitivity

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Solution Overview

Problem

Conventional chip packages with sensing functions, such as fingerprint-recognition chips, face challenges due to the thickness of the encapsulant layer affecting sensitivity and the risk of short circuits from protruding wires, which reduces yield and structural strength.

Innovation Solution

A chip package design featuring a sensing region with first openings exposing conductive extending portions that electrically connect to sensing units, allowing these portions to extend onto the chip surface, reducing the encapsulant layer thickness and improving sensitivity while maintaining structural strength by forming shallow recess structures to accommodate wires without increasing substrate removal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the encapsulant layer thickness is reduced to improve sensing sensitivity, then the sensitivity of the sensing region is improved, but the structural strength and protection capability are compromised

Engineering Contradiction:
Improvesensing sensitivityVSAvoidstructural strength
Core Design Contradiction:
Measurement precisionVSStrength

Solution Approach 1:

The patent applies local quality by creating a recess structure specifically at the sensing region to reduce encapsulant thickness only where needed for sensitivity, while maintaining normal encapsulant thickness in other regions to preserve structural strength and protection capability.

Inventive Principle:
Principle #3Local quality

2Reliability

If wires are bonded from the contact pad region to the printed circuit board, then electrical connection is established, but the wires protrude from the chip surface causing short circuits or broken circuits that reduce yield

Engineering Contradiction:
Improveelectrical connectionVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies the nesting principle by placing the wires inside a recess structure that is formed within the encapsulant layer. This recess accommodates the protruding wires, preventing them from contacting the chip edges and causing short circuits or broken circuits during bonding, thereby improving manufacturing yield while maintaining electrical connection reliability.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Strength

If the side height of the periphery of the packaged chip is increased to protect the sensing region, then the structural protection is improved, but the overall chip height increases affecting packaging compactness

Engineering Contradiction:
Improveprotection capabilityVSAvoidchip height
Core Design Contradiction:
StrengthVSLength of stationary object

Solution Approach 1:

The patent applies segmentation by dividing the encapsulant layer into different regions: a recessed sensing region with reduced thickness for sensitivity, and a higher peripheral region for protection. This segmented structure provides the necessary protection capability while avoiding an overall increase in chip height, as the protection is achieved through localized height variation rather than uniform height increase.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9437478B2Chip package and method for forming the same
Publication Date: 2016.09.06 XINTEC INC
  • US9437478B2 patent drawing
  • US9437478B2 patent drawing
  • US9437478B2 patent drawing

AI summary

A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.