Chip Package Shallow Recess for Wire Bonding
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Solution Overview
Problem
Conventional chip packages with sensing functions, such as fingerprint-recognition chips, face challenges due to the thickness of the encapsulant layer, which affects sensitivity and can lead to short or broken circuits during the bonding process, preventing the formation of a flat surface.
Innovation Solution
A chip package design featuring a shallow recess structure outside the signal pad region, with a redistribution layer connected to the signal pad and a wire bonded to the redistribution layer within the recess, allowing for reduced encapsulant layer thickness and improved sensitivity while maintaining structural strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires are bonded from contact pad region to printed circuit board, then electrical connection is established, but encapsulant layer thickness increases and sensitivity decreases
Solution Approach 1:
The patent moves the wire bonding location from the upper surface (contact pad region) to the side surface of the chip, utilizing the vertical dimension. This allows wires to be bonded at a lower height relative to the upper surface, enabling thinner encapsulant layers while maintaining electrical connection reliability.
Solution Approach 2:
The patent introduces a shallow recess structure as an intermediary feature on the chip surface. This recess provides a dedicated location for wire bonding that is lower than the contact pad region, acting as a mediator between the electrical connection requirement and the sensitivity requirement.
2Reliability
If wires are bonded adjacent to chip edges, then electrical connection is achieved, but short circuit or broken circuit risk increases
Solution Approach 1:
The patent creates a localized shallow recess structure with specific geometric properties (depth, width, positioning) that differs from the surrounding chip surface. This local modification provides a protected environment for wire bonding, isolating the wires from harmful contact with chip edges while maintaining electrical connectivity.
3Measurement precision
If encapsulant layer thickness is reduced, then sensitivity improves, but wire bonding becomes more difficult
Solution Approach 1:
The shallow recess structure is formed on the chip surface before wire bonding takes place. This preliminary preparation creates a pre-positioned, protected location for wire placement, making the subsequent wire bonding process easier and more reliable even when the overall encapsulant layer is thin.
Data Source
AI summary
A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.