Chip Package Shielding Film Layout for Compact EMI Protection

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Solution Overview

Problem

The challenge of forming reliable semiconductor devices at smaller sizes due to the increasing complexity and difficulty of fabrication processes in the semiconductor integrated circuit (IC) industry, where feature sizes continue to decrease.

Innovation Solution

A chip package structure is developed with a conductive shielding film that includes a conductive shielding material layer conformally covering the chip package structures, providing electromagnetic interference (EMI) shielding and reducing the size of the redistribution structure by overlapping grounding bumps with seal rings, thereby enhancing structural integrity and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the chip package structure into multiple functional layers including conductive shielding film layer, mold compound layer, substrate layer, and interconnection structures. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall miniaturization, thereby improving production efficiency without excessively complicating the fabrication process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar layouts to three-dimensional stacked architectures by implementing vertical interconnection structures, through-substrate vias, and multi-layer shielding films. This dimensional change increases functional density without proportionally increasing fabrication complexity, as the vertical integration consolidates multiple functions into a compact stack.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If feature sizes continue to decrease, then production efficiency is improved, but manufacturing reliability deteriorates

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements conductive shielding films and ground structures before final packaging to preemptively protect sensitive interconnection structures from EMI and moisture. This beforehand protection prevents reliability issues before they occur, allowing smaller feature sizes to be manufactured with maintained reliability by cushioning against environmental and electromagnetic stresses.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent employs composite material structures combining conductive shielding materials (copper, aluminum, or conductive polymer) with insulating mold compounds and substrate materials. These composite structures provide both mechanical protection and electromagnetic shielding, enabling reliable operation of miniaturized features by protecting them from degradation while maintaining compact dimensions.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The conductive shielding film effectively reduces the size of the chip package structure while providing EMI shielding, improving reliability and protection against damage and moisture degradation.

Implementation Method 1

providing electromagnetic interference (EMI) shielding

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS12489089B2Chip package structure with conductive shielding film
Publication Date: 2025.12.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12489089B2 patent drawing
  • US12489089B2 patent drawing
  • US12489089B2 patent drawing

AI summary

A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.