Chip Package Sidewall Conductive Extension for Cost Reduction
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Solution Overview
Problem
The existing chip package manufacturing process is limited by the size of the silicon chip, making it difficult to reduce material costs and adjust package size, and requires an etching process to expose conductive pads, increasing fabrication costs.
Innovation Solution
A chip package design that includes a molding material covering the rear and sidewall of the chip structure, allowing the conductive layer to extend from the conductive pad to the molding material, and a redistribution layer that connects to the conductive layer without needing an additional isolation layer, thereby omitting the etching process and enabling size adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the chip package size is determined by the silicon chip size, then the chip structure is simple, but the package size cannot be adjusted and material cost cannot be reduced
Solution Approach 1:
The patent extends the conductive layer and redistribution layer from the traditional planar configuration onto the sidewall of the chip package. The conductive layer extends from the conductive pad on the front surface along the sidewall to the rear surface, creating a three-dimensional electrical connection path. This dimensional transition enables independent adjustment of package size from chip size while maintaining electrical connectivity through the sidewall extension structure.
2Reliability
If an etching process is performed to form a trench and expose the conductive pad, then electrical connection is ensured, but fabrication cost increases
Solution Approach 1:
The conductive layer is formed to extend onto the sidewall of the chip package before the redistribution layer is deposited. This preliminary formation of the conductive layer on the sidewall eliminates the need for subsequent etching processes to expose conductive pads, as the conductive connection is already established through the sidewall extension. The sequence of operations is optimized to prevent the need for costly etching steps.
3Reliability
If an isolation layer is formed to cover the rear surface and sidewall, then short circuiting is prevented, but fabrication cost increases
Solution Approach 1:
The patent removes the isolation layer from the structure by utilizing the molding compound to directly cover the rear surface and sidewall of the chip package. The molding compound serves as both the encapsulation material and the isolation medium, eliminating the need for a separate isolation layer. This extraction of the isolation function to the molding compound reduces fabrication steps and costs while maintaining electrical isolation and preventing short circuits.
Data Source
AI summary
A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.