Chip Package Assembly Solder Resist Crack Resistance
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Solution Overview
Problem
The reliability of solder connections in flip-chip mounting is compromised due to solder resist cracking, which can lead to poor performance and failure, especially during the reflow process, causing electrical shorting and solder wicking issues.
Innovation Solution
The implementation of offsetting solder pads and pillars, and forming trenches in the solder resist around solder pads, to reduce stress and prevent cracking, ensuring improved alignment and resilience of solder connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder pads are aligned directly with pillars (zero offset), then manufacturing precision is improved, but solder resist cracking occurs during reflow due to stress concentration
Solution Approach 1:
The patent introduces an asymmetric offset design where solder pads are deliberately misaligned with pillars by a controlled distance (e.g., 0.05-0.15mm). This asymmetric positioning redistributes thermal stress away from the solder resist-solder interface, preventing crack formation while maintaining electrical connectivity through the offset compensation mechanism during reflow heating.
Solution Approach 2:
The offset is pre-designed and built into the PCB layout before the reflow process. This preliminary geometric compensation anticipates the thermal expansion that will occur during soldering, ensuring that stress concentrations are avoided from the outset rather than attempting to prevent cracks after they form.
2Strength
If solder pads are offset from pillars, then solder resist crack resistance is improved, but alignment precision deteriorates
Solution Approach 1:
The patent optimizes the offset parameter within a specific range (0.05-0.15mm) to balance crack resistance and alignment precision. By carefully controlling this parameter, the design achieves sufficient stress redistribution to prevent cracking while maintaining acceptable alignment for reliable solder joint formation through the self-aligning effect during reflow.
Data Source
AI summary
A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.