Chip Package Spacers for Adhesive Control
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Solution Overview
Problem
Conventional chip packages experience poor connections and yield issues due to the softness of silver epoxy, leading to spillage and tilting of chips during the wire bonding process, which compromises the reliability and efficiency of the chip package process.
Innovation Solution
The introduction of spacers, such as metal balls or protuberances, between the chip and the package substrate maintains an interval and supports the chip, preventing adhesive layer spillage and ensuring stable deposition, while an adhesive layer encapsulates the spacers and wires connect the chip to the substrate, enhancing connection intensity and process yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If silver epoxy is used to adhere the chip to the package substrate, then the chip can be attached to the substrate, but the softness of the silver epoxy causes spillage during wire bonding and makes thickness control difficult
Solution Approach 1:
The adhesive system is segmented into two functional components: rigid spacers that provide precise thickness control and positioning, and silver epoxy that provides adhesion. This segmentation allows each component to optimize its specific function without compromising the other.
Solution Approach 2:
The spacers are placed on the package substrate before chip mounting. This preliminary action establishes the exact thickness and positioning requirements before the chip is attached, preventing thickness control issues during the adhesion process.
2Strength
If silver epoxy is used to adhere the chip, then the chip can be attached to the substrate, but the chip tilts during deposition because thickness control is difficult
Solution Approach 1:
The adhesive system is segmented into two functional components: rigid spacers that provide precise thickness control and positioning, and silver epoxy that provides adhesion. This segmentation allows each component to optimize its specific function without compromising the other.
Solution Approach 2:
The spacers are placed on the package substrate before chip mounting. This preliminary action establishes the exact thickness and positioning requirements before the chip is attached, preventing thickness control issues during the adhesion process.
3Reliability
If wire bonding is performed under pressure, then electrical connection can be established, but the soft silver epoxy spills from the periphery of the chip
Solution Approach 1:
The rigid spacers act as a cushioning structure that prevents the silver epoxy from being forced outward during wire bonding pressure application. By providing a rigid barrier, the spacers contain the adhesive material and prevent spillage while allowing the necessary pressure for reliable wire bonding.
4Ease of manufacture
If the thickness of silver epoxy is not controlled, then the chip can be attached to the substrate, but the yield of the chip package process is lowered
Solution Approach 1:
The spacers are placed on the package substrate before chip mounting. This preliminary action establishes the exact thickness and positioning requirements before the chip is attached, preventing thickness control issues during the adhesion process.
Solution Approach 2:
The manual or less precise thickness control methods are replaced with a mechanical spacer system that provides automatic, precise thickness control. This substitution eliminates variability in adhesive thickness and improves manufacturing yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of spacers effectively prevents adhesive layer spillage, stabilizes chip deposition, and improves connection reliability, thereby enhancing the yield and reliability of the chip package process.
Implementation Method 1
The adhesive layer is disposed between the chip and the carrying surface to encapsulate the spacers
Data Source
AI summary
A chip package and a package process thereof are provided. The chip package comprises a package substrate, a chip, a plurality of spacers, an adhesive layer, and a plurality of wires. The package substrate has a carrying surface. The chip is disposed on the carrying surface. The spacers are formed between the chip and the carrying surface to maintain an interval between the chip and the package substrate. The adhesive layer is disposed between the chip and carrying surface to encapsulate the spacers. The chip is electrically connected to the package substrate via the wires.


