Chip Package Spacing Layer Auxiliary Pattern for CTE Mismatch
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Solution Overview
Problem
The CTE mismatch between semiconductor substrates and glass substrates in wafer level packaging leads to reliability issues and delamination in chip packages, allowing moisture or air to enter and affect electrical performance.
Innovation Solution
A chip package design that includes a semiconductor substrate with a device region, a package layer, a spacing layer surrounding the device region, and an auxiliary pattern such as a hollow pattern or material pattern between the spacing layer and the device region, which helps to reduce stress and improve adhesion, thereby enhancing package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spacing layer is used to bond semiconductor substrate to glass substrate, then the chip package can be formed with proper spacing, but CTE mismatch causes delamination and reduces reliability
Solution Approach 1:
The patent introduces an auxiliary pattern (hollow pattern or material pattern) at specific locations within the spacing layer to create local structural variations. This local quality change allows the spacing layer to have different mechanical properties in different regions, accommodating CTE mismatch stresses while maintaining overall adhesion stability and preventing delamination.
Solution Approach 2:
The patent modifies the structural parameters of the spacing layer by introducing hollow patterns (changing void volume and distribution) or material patterns (changing material composition and density). These parameter changes enable the spacing layer to better accommodate thermal expansion differences between substrates, reducing stress and improving reliability without sacrificing adhesion.
2Reliability
If CTE mismatch is not addressed, then manufacturing is simple, but moisture or air enters the package and electrical performance deteriorates
Solution Approach 1:
The auxiliary pattern creates localized structural features within the spacing layer that improve the overall hermetic sealing. The hollow or material patterns modify stress distribution locally, preventing delamination pathways that would otherwise allow moisture and air to penetrate, thus protecting electrical performance without complicating the overall manufacturing process.
3Reliability
If auxiliary pattern is added to reduce stress, then adhesion improves, but device complexity increases
Solution Approach 1:
The auxiliary pattern segments the spacing layer structure by introducing hollow regions or material patterns at specific locations. This segmentation approach allows stress management through distributed structural features rather than requiring complete redesign of the entire spacing layer, thereby improving adhesion while limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The auxiliary pattern reduces stress and improves adhesion between the spacing layer and the substrate, leading to increased reliability and yield of the chip package process, allowing for hermetic sealing and improved electrical performance.
Implementation Method 1
The CTE (coefficient of thermal expansion) mismatch between the semiconductor substrate, the spacing layer and the glass substrate causes reliability problems or even delamination of the chip package as the spacing layer cannot tightly adhere to the semiconductor substrate and/or the glass substrate
Data Source
AI summary
An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.