Chip Package Lead Frame with Stacked Metal Layers for Heat Dissipation
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Solution Overview
Problem
Conventional lead-frame based chip packages face challenges with miniaturization, leading to increased wire bonding distances and lengths, which can result in short circuits and reduced heat dissipation efficiency due to insulation requirements between the chip pad and leads, increasing production costs and thermal impedance.
Innovation Solution
A chip package structure with a lead frame featuring a first patterned metal layer with a chip pad and bonding pads separated by grooves, and a second patterned metal layer with a heat dissipation block and terminal pads also separated by grooves, allowing bonding pads to extend closer to the chip periphery and increasing the heat dissipation area by enlarging the heat dissipation block dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip size is reduced to achieve miniaturization, then the chip becomes more compact and modern electronic devices can be lighter and slimmer, but the distance between the chip and the inner leads of the lead frame increases, requiring longer bonding wires that are prone to collapse and breakage
Solution Approach 1:
The patent transitions from a planar lead frame structure to a three-dimensional stacked structure where bonding pads are positioned vertically above the chip pad through multiple metal layers. This dimensional change allows bonding wires to connect to pads closer to the chip while maintaining electrical connectivity, thereby reducing wire length and improving reliability without compromising miniaturization benefits.
Solution Approach 2:
The lead frame is segmented into multiple functional metal layers (first patterned metal layer with bonding pads, second patterned metal layer with terminal pads) separated by insulation layers. This segmentation allows different regions to serve specialized functions: the first layer provides bonding pads positioned optimally for wire bonding, while the second layer provides terminal pads for external connections, enabling independent optimization of each function.
2Reliability
If insulation spacing is maintained between the chip pad and leads to prevent electrical short circuits, then electrical insulation is ensured, but the heat dissipation area of the chip pad is limited
Solution Approach 1:
The electrical insulation function is segmented from the heat dissipation function by creating separate metal layers. The first patterned metal layer contains bonding pads electrically insulated from the chip pad, while the second patterned metal layer contains terminal pads that can be thermally coupled to the chip pad through thermal vias or direct thermal pathways, allowing heat dissipation without compromising electrical insulation.
Solution Approach 2:
The patent uses vertical stacking of metal layers to resolve the conflict between electrical insulation and heat dissipation. By moving terminal pads to a second metal layer above the chip pad, the design maintains horizontal electrical insulation while establishing vertical thermal pathways through the insulation layer via thermal vias, enabling heat dissipation in the vertical dimension without compromising electrical isolation in the horizontal plane.
3Productivity
If bonding pads are positioned closer to the chip periphery to reduce wire bonding distance, then wire length is reduced and yield improves, but the bonding pads may interfere with the insulation layer structure
Solution Approach 1:
The lead frame structure is divided into distinct functional layers: the first patterned metal layer contains bonding pads positioned close to the chip pad for optimal wire bonding, while the insulation layer and second metal layer are structured to accommodate this positioning. This segmentation allows each layer to be optimized independently for its specific function without compromising overall structure.
Solution Approach 2:
The insulation layer is pre-configured with openings or vias at predetermined locations where bonding pads will be positioned, and thermal pathways are pre-established through the insulation layer. This preliminary structuring of the insulation layer eliminates potential interference issues and simplifies subsequent bonding pad placement and wire bonding operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces wire bonding distances, improves yield, and enhances heat dissipation efficiency by increasing the heat dissipation area while simplifying the packaging process and reducing production costs by eliminating the need for additional insulation during molding.
Implementation Method 1
The heat dissipation block is thermally coupled to the chip pad
Data Source
AI summary
A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.