Chip Package With Stacked Substrates And Exposed Sensing Regions
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Solution Overview
Problem
Current multi-chip package technologies face challenges in achieving high performance, functionality, and efficient integration of semiconductor chips in a compact and lightweight form, particularly in creating effective electrical connections and sensing regions within chip packages.
Innovation Solution
A chip package structure is developed, featuring a first substrate with a second substrate bonded on top, including a lower semiconductor layer, an upper semiconductor layer, and an insulating layer, with a conducting layer and protection layer to form electrical connections and expose sensing regions, allowing for efficient electrical contact and sensing applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a single package to achieve multi-functionality, then device functionality is improved, but device complexity increases
Solution Approach 1:
The package structure is divided into distinct functional layers: first substrate for electrical connections, second substrate for sensing elements, and intermediate bonding layer. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall system integration.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, placing the second substrate vertically above the first substrate. This dimensional change enables multi-functionality within a compact footprint while simplifying inter-chip connections through vertical bonding interfaces.
2Volume of moving object
If chip package size is reduced to meet compact device requirements, then device portability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The smaller second substrate containing sensing elements is nested within the overall package structure defined by the first substrate. This nested configuration maximizes space utilization and minimizes the external package dimensions while maintaining proper alignment through the bonding interface.
Solution Approach 2:
The intermediate bonding layer serves as a mediator between the first and second substrates, providing both mechanical support and electrical connection. This intermediary layer absorbs alignment tolerances and facilitates precise positioning of the second substrate relative to the first substrate during the bonding process.
3Reliability
If electrical connections are made between substrates to improve connectivity, then electrical conductivity is improved, but device complexity increases
Solution Approach 1:
The bonding layer performs dual functions simultaneously: it provides mechanical bonding between substrates and establishes electrical connections through integrated conductive pathways. This merging of mechanical and electrical functions into a single layer reduces the number of separate components and simplifies the overall connection structure.
Solution Approach 2:
The bonding layer is designed as a multi-functional element that accomplishes both substrate attachment and electrical signal transmission. This universal component eliminates the need for separate mechanical fasteners and electrical interconnects, thereby reducing structural complexity while maintaining reliable electrical connectivity.
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.